uart: rockchip: add uart supported for rk3228

Change-Id: I86b49f20954a739645b9277e45d6b75058ff9c2b
Signed-off-by: David Wu <wdc@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index 4b735c0d1d7250579d1828a31ed867fe80caa32e..ef13aadb9a77d1842a7fad3e8bb0c75f8a3a6025 100644 (file)
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -12,7 +12,9 @@
        interrupt-parent = <&gic>;
 
        aliases {
-               serial2 = &uart_dbg;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
@@ -103,18 +105,6 @@
                clock-frequency = <24000000>;
        };
 
-       uart_dbg: serial@11030000 {
-               compatible = "rockchip,serial";
-               reg = <0x11030000 0x100>;
-               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-               clock-frequency = <24000000>;
-               clocks = <&xin24m>, <&xin24m>;
-               clock-names = "sclk_uart", "pclk_uart";
-               reg-shift = <2>;
-               reg-io-width = <4>;
-               status = "disabled";
-       };
-
        fiq-debugger {
                compatible = "rockchip,fiq-debugger";
                rockchip,serial-id = <2>;
@@ -203,6 +193,54 @@
                        <&clk_gates1 3>;/*clk_jtag*/
        };
 
+       uart0: serial@11010000 {
+               compatible = "rockchip,serial";
+               reg = <0x11010000 0x100>;
+               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+               clock-frequency = <24000000>;
+               clocks = <&clk_uart0>, <&clk_gates9 12>;
+               clock-names = "sclk_uart", "pclk_uart";
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               dmas = <&pdma 2>, <&pdma 3>;
+               #dma-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+               status = "disabled";
+       };
+
+       uart1: serial@11020000 {
+               compatible = "rockchip,serial";
+               reg = <0x11020000 0x100>;
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+               clock-frequency = <24000000>;
+               clocks = <&clk_uart1>, <&clk_gates9 13>;
+               clock-names = "sclk_uart", "pclk_uart";
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               dmas = <&pdma 4>, <&pdma 5>;
+               #dma-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+               status = "disabled";
+       };
+
+       uart2: serial@11030000 {
+               compatible = "rockchip,serial";
+               reg = <0x11030000 0x100>;
+               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               clock-frequency = <24000000>;
+               clocks = <&clk_uart2>, <&clk_gates9 14>;
+               lock-names = "sclk_uart", "pclk_uart";
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               dmas = <&pdma 6>, <&pdma 7>;
+               #dma-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart2_xfer>;
+               status = "disabled";
+       };
+
        i2c0: i2c@11050000 {
                compatible = "rockchip,rk30-i2c";
                reg = <0x11050000 0x1000>;