tblgen autogens this pattern now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23530 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 46ccd639ba978e09d39a2df5edb4f2c2bc67da65..41ad2244664a66db59a8035da21ed9ee62cd3eb5 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -796,16 +796,10 @@ def RLDICR : MDForm_1<30, 1,
 def : Pat<(i32 imm:$imm),
           (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
 
-
 // Implement the 'not' operation with the NOR instruction.
 def NOT : Pat<(not GPRC:$in),
               (NOR GPRC:$in, GPRC:$in)>;
 
-// EQV patterns
-// FIXME: This should be autogenerated from the above due to xor association.
-def EQV1 : Pat<(xor (not GPRC:$in1), GPRC:$in2),
-               (EQV GPRC:$in1, GPRC:$in2)>;
-
 // ADD an arbitrary immediate.
 def : Pat<(add GPRC:$in, imm:$imm),
           (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;