Moved code to modify the opcode from 'reg' to 'imm' form to a more logical place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6563 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
index 268fb3d877c432197826876241772aea5efc2302..f654e90100bb8742960779c610eb353948d61408 100644 (file)
--- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
@@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
                                       immedValue);
             if (opType == MachineOperand::MO_VirtualRegister)
               constantThatMustBeLoaded = true;
-            else {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
           }
         }
       else
@@ -219,21 +213,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
                 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
                 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
             }
-          else 
-            {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
         }
 
       if (opType == MachineOperand::MO_MachineRegister)
         minstr->SetMachineOperandReg(op, machineRegNum);
       else if (opType == MachineOperand::MO_SignExtendedImmed ||
-               opType == MachineOperand::MO_UnextendedImmed)
+               opType == MachineOperand::MO_UnextendedImmed) {
         minstr->SetMachineOperandConst(op, opType, immedValue);
-      else if (constantThatMustBeLoaded ||
+        // The optype has changed from being a register to an immediate
+        // This means we need to change the opcode, e.g. ADDr -> ADDi
+        unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+        minstr->setOpcode(newOpcode);
+      } else if (constantThatMustBeLoaded ||
                (opValue && isa<GlobalValue>(opValue)))
         { // opValue is a constant that must be explicitly loaded into a reg
           assert(opValue);

diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index 268fb3d877c432197826876241772aea5efc2302..f654e90100bb8742960779c610eb353948d61408 100644 (file)
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
                                       immedValue);
             if (opType == MachineOperand::MO_VirtualRegister)
               constantThatMustBeLoaded = true;
-            else {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
           }
         }
       else
@@ -219,21 +213,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
                 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
                 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
             }
-          else 
-            {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
         }
 
       if (opType == MachineOperand::MO_MachineRegister)
         minstr->SetMachineOperandReg(op, machineRegNum);
       else if (opType == MachineOperand::MO_SignExtendedImmed ||
-               opType == MachineOperand::MO_UnextendedImmed)
+               opType == MachineOperand::MO_UnextendedImmed) {
         minstr->SetMachineOperandConst(op, opType, immedValue);
-      else if (constantThatMustBeLoaded ||
+        // The optype has changed from being a register to an immediate
+        // This means we need to change the opcode, e.g. ADDr -> ADDi
+        unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+        minstr->setOpcode(newOpcode);
+      } else if (constantThatMustBeLoaded ||
                (opValue && isa<GlobalValue>(opValue)))
         { // opValue is a constant that must be explicitly loaded into a reg
           assert(opValue);