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I really didn't think this was necessary. But, Legalize wasn't running again
author
Andrew Lenharth
<andrewl@lenharth.org>
Sat, 2 Jul 2005 20:58:53 +0000
(20:58 +0000)
committer
Andrew Lenharth
<andrewl@lenharth.org>
Sat, 2 Jul 2005 20:58:53 +0000
(20:58 +0000)
and legalizing the extload. Strange. Should fix most alpha regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22329
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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diff --git
a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9a2740457f0ab105cc13702ef0d2b0cfa3ab983c..51375c5c8eed4783360c400b7f21bf08f3616dd8 100644
(file)
--- a/
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@
-1351,8
+1351,9
@@
SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
DAG.getSrcValue(NULL));
else {
assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
- FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
- CPIdx, DAG.getSrcValue(NULL), MVT::f32);
+ FudgeInReg =
+ LegalizeOp(DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+ CPIdx, DAG.getSrcValue(NULL), MVT::f32));
}
Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
break;