Update.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index dd65dd9fc343eee9a01ce57e14a75812086000de..e95b4c1d68a6fb82969bab2b167130184b772193 100644 (file)
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -199,8 +199,8 @@ void ARMConstantIslands::verify(MachineFunction &Fn) {
 /// print block size and offset information - debugging
 void ARMConstantIslands::dumpBBs() {
   for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
-    DOUT << "block" << J << " offset" << BBOffsets[J] << 
-                            " size" << BBSizes[J] << "\n";
+    DOUT << "block " << J << " offset " << BBOffsets[J] << 
+                            " size " << BBSizes[J] << "\n";
   }
 }
 
@@ -255,10 +255,10 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &Fn) {
     bool Change = false;
     for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
       Change |= HandleConstantPoolUser(Fn, i);
-    DEBUG(dumpBBs());
+    //DEBUG(dumpBBs());
     for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
       Change |= FixUpImmediateBr(Fn, ImmBranches[i]);
-    DEBUG(dumpBBs());
+    //DEBUG(dumpBBs());
     if (!Change)
       break;
     MadeChange = true;
@@ -798,8 +798,8 @@ int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
   MachineInstr *CPEMI  = U.CPEMI;
 
   // Check to see if the CPE is already in-range.
-  if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, true)) {
-    DOUT << "In range\n";
+  if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, false /*true*/)) {
+    //DOUT << "In range\n";
     return 1;
   }
 
@@ -1120,11 +1120,13 @@ bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
   unsigned BrOffset   = GetOffsetOf(MI) + PCAdj;
   unsigned DestOffset = BBOffsets[DestBB->getNumber()];
 
+#if 0
   DOUT << "Branch of destination BB#" << DestBB->getNumber()
        << " from BB#" << MI->getParent()->getNumber()
        << " max delta=" << MaxDisp
        << " from " << GetOffsetOf(MI) << " to " << DestOffset
        << " offset " << int(DestOffset-BrOffset) << "\t" << *MI;
+#endif
 
   if (BrOffset <= DestOffset) {
     // Branch before the Dest.

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index c30c0e5a9ff6151b1fcb0ad8dc2ab5edf635ae49..3db8f54f50ca1319e37e18beca1d7fac5829d180 100644 (file)
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -7,7 +7,6 @@ Reimplement 'select' in terms of 'SEL'.
 * We would really like to support UXTAB16, but we need to prove that the
   add doesn't need to overflow between the two 16-bit chunks.
 
-* implement predication support
 * Implement pre/post increment support.  (e.g. PR935)
 * Coalesce stack slots!
 * Implement smarter constant generation for binops with large immediates.
@@ -44,16 +43,12 @@ consecutive islands as a single block rather than multiple blocks.
 
 //===---------------------------------------------------------------------===//
 
-We need to start generating predicated instructions.  The .td files have a way
-to express this now (see the PPC conditional return instruction), but the 
-branch folding pass (or a new if-cvt pass) should start producing these, at
-least in the trivial case.
+Eliminate copysign custom expansion. We are still generating crappy code with
+default expansion + if-conversion.
 
-Among the obvious wins, doing so can eliminate the need to custom expand 
-copysign (i.e. we won't need to custom expand it to get the conditional
-negate).
+//===---------------------------------------------------------------------===//
 
-This allows us to eliminate one instruction from:
+Eliminate one instruction from:
 
 define i32 @_Z6slow4bii(i32 %x, i32 %y) {
         %tmp = icmp sgt i32 %x, %y
@@ -66,6 +61,12 @@ __Z6slow4bii:
         movgt r1, r0
         mov r0, r1
         bx lr
+=>
+
+__Z6slow4bii:
+        cmp r0, r1
+        movle r0, r1
+        bx lr
 
 //===---------------------------------------------------------------------===//