Fix a bug in the soft-float handling of FCOPYSIGN that Duncan noticed

when working on legalizetypes.  Both legalizetypes and legalizeops now
produce hte same code for CodeGen/ARM/fcopysign.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53435 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 80502cfe698f1523c3d2ac24bbbcf38367a50ab5..4b4c02bd8d82ae48ce89ae8d16502e7bd1e605b9 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -547,8 +547,11 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
     SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
                           DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
     SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
-  } else if (SizeDiff < 0)
-    SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
+  } else if (SizeDiff < 0) {
+    SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
+    SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
+                          DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
+  }
 
   // Clear the sign bit of first operand.
   SDOperand Mask2 = (VT == MVT::f64)