* author: zyw@rock-chips.com\r
*****************************************************************************************/\r
//#ifdef CONFIG_LCD_TD043MGEA1\r
-#define LCD_TXD_PIN RK29_PIN0_PA6 // ÂÒÌî,µÃÐÞ¸Ä\r
-#define LCD_CLK_PIN RK29_PIN0_PA7 // ÂÒÌî,µÃÐÞ¸Ä\r
-#define LCD_CS_PIN RK29_PIN0_PB6 // ÂÒÌî,µÃÐÞ¸Ä\r
-#define LCD_TXD_MUX_NAME GPIOE_U1IR_I2C1_NAME\r
-#define LCD_CLK_MUX_NAME NULL\r
-#define LCD_CS_MUX_NAME GPIOH6_IQ_SEL_NAME\r
-#define LCD_TXD_MUX_MODE 0\r
-#define LCD_CLK_MUX_MODE 0\r
-#define LCD_CS_MUX_MODE 0\r
+#define LCD_TXD_PIN INVALID_GPIO\r
+#define LCD_CLK_PIN INVALID_GPIO\r
+#define LCD_CS_PIN INVALID_GPIO\r
+/*****************************************************************************************\r
+* frame buffe devices\r
+* author: zyw@rock-chips.com\r
+*****************************************************************************************/\r
+#define FB_ID 0\r
+#define FB_DISPLAY_ON_PIN RK29_PIN6_PD0\r
+#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1\r
+#define FB_MCU_FMK_PIN INVALID_GPIO\r
+\r
+#define FB_DISPLAY_ON_VALUE GPIO_HIGH\r
+#define FB_LCD_STANDBY_VALUE GPIO_HIGH\r
+\r
//#endif\r
static int rk29_lcd_io_init(void)\r
{\r
int ret = 0;\r
-\r
-#if 0\r
- rk29_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE);\r
- if (LCD_CS_PIN != INVALID_GPIO) {\r
- ret = gpio_request(LCD_CS_PIN, NULL);\r
- if(ret != 0)\r
- {\r
- goto err1;\r
- printk(">>>>>> lcd cs gpio_request err \n ");\r
- }\r
- }\r
-\r
- rk29_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE);\r
- if (LCD_CLK_PIN != INVALID_GPIO) {\r
- ret = gpio_request(LCD_CLK_PIN, NULL);\r
- if(ret != 0)\r
- {\r
- goto err2;\r
- printk(">>>>>> lcd clk gpio_request err \n ");\r
- }\r
- }\r
-\r
- rk29_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE);\r
- if (LCD_TXD_PIN != INVALID_GPIO) {\r
- ret = gpio_request(LCD_TXD_PIN, NULL);\r
- if(ret != 0)\r
- {\r
- goto err3;\r
- printk(">>>>>> lcd txd gpio_request err \n ");\r
- }\r
- }\r
-\r
- return 0;\r
-\r
-err3:\r
- if (LCD_CLK_PIN != INVALID_GPIO) {\r
- gpio_free(LCD_CLK_PIN);\r
- }\r
-err2:\r
- if (LCD_CS_PIN != INVALID_GPIO) {\r
- gpio_free(LCD_CS_PIN);\r
- }\r
-err1:\r
-#endif\r
return ret;\r
}\r
\r
static int rk29_lcd_io_deinit(void)\r
{\r
int ret = 0;\r
-#if 0\r
- gpio_direction_output(LCD_CLK_PIN, 0);\r
- gpio_set_value(LCD_CLK_PIN, GPIO_HIGH);\r
- gpio_direction_output(LCD_TXD_PIN, 0);\r
- gpio_set_value(LCD_TXD_PIN, GPIO_HIGH);\r
-\r
- gpio_free(LCD_CS_PIN);\r
- rk29_mux_api_mode_resume(LCD_CS_MUX_NAME);\r
- gpio_free(LCD_CLK_PIN);\r
- gpio_free(LCD_TXD_PIN);\r
- rk29_mux_api_mode_resume(LCD_TXD_MUX_NAME);\r
- rk29_mux_api_mode_resume(LCD_CLK_MUX_NAME);\r
-#endif\r
return ret;\r
}\r
\r
struct rk29lcd_info rk29_lcd_info = {\r
- //.txd_pin = LCD_TXD_PIN,\r
- //.clk_pin = LCD_CLK_PIN,\r
- //.cs_pin = LCD_CS_PIN,\r
+ .txd_pin = LCD_TXD_PIN,\r
+ .clk_pin = LCD_CLK_PIN,\r
+ .cs_pin = LCD_CS_PIN,\r
.io_init = rk29_lcd_io_init,\r
.io_deinit = rk29_lcd_io_deinit,\r
};\r
\r
\r
-/*****************************************************************************************\r
- * frame buffe devices\r
- * author: zyw@rock-chips.com\r
- *****************************************************************************************/\r
-\r
-#define FB_ID 0\r
-#define FB_DISPLAY_ON_PIN RK29_PIN0_PB1 // ÂÒÌî,µÃÐÞ¸Ä\r
-#define FB_LCD_STANDBY_PIN INVALID_GPIO\r
-#define FB_MCU_FMK_PIN INVALID_GPIO\r
-\r
-#if 0\r
-#define FB_DISPLAY_ON_VALUE GPIO_LOW\r
-#define FB_LCD_STANDBY_VALUE 0\r
-\r
-#define FB_DISPLAY_ON_MUX_NAME GPIOB1_SMCS1_MMC0PCA_NAME\r
-#define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B1\r
-\r
-#define FB_LCD_STANDBY_MUX_NAME NULL\r
-#define FB_LCD_STANDBY_MUX_MODE 1\r
-\r
-#define FB_MCU_FMK_PIN_MUX_NAME NULL\r
-#define FB_MCU_FMK_MUX_MODE 0\r
-\r
-#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME\r
-#define FB_DATA0_16_MUX_MODE 1\r
-\r
-#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME\r
-#define FB_DATA17_18_MUX_MODE 1\r
-\r
-#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME\r
-#define FB_DATA19_24_MUX_MODE 1\r
-\r
-#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME\r
-#define FB_DEN_MUX_MODE 1\r
-\r
-#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME\r
-#define FB_VSYNC_MUX_MODE 1\r
-\r
-#define FB_MCU_FMK_MUX_NAME NULL\r
-#define FB_MCU_FMK_MUX_MODE 0\r
-#endif\r
static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)\r
{\r
int ret = 0;\r
-#if 0\r
- if(fb_setting->data_num <=16)\r
- rk29_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE);\r
- if(fb_setting->data_num >16 && fb_setting->data_num<=18)\r
- rk29_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE);\r
- if(fb_setting->data_num >18)\r
- rk29_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE);\r
-\r
- if(fb_setting->vsync_en)\r
- rk29_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE);\r
-\r
- if(fb_setting->den_en)\r
- rk29_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE);\r
-\r
- if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO))\r
+ if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))\r
{\r
- rk29_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE);\r
ret = gpio_request(FB_MCU_FMK_PIN, NULL);\r
if(ret != 0)\r
{\r
}\r
gpio_direction_input(FB_MCU_FMK_PIN);\r
}\r
-\r
- if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO))\r
+ if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))\r
{\r
- rk29_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE);\r
ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);\r
if(ret != 0)\r
{\r
}\r
}\r
\r
- if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO))\r
+ if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))\r
{\r
- rk29_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE);\r
ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);\r
if(ret != 0)\r
{\r
printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");\r
}\r
}\r
-#endif\r
return ret;\r
}\r
\r
struct rk29fb_info rk29_fb_info = {\r
.fb_id = FB_ID,\r
- //.disp_on_pin = FB_DISPLAY_ON_PIN,\r
- //.disp_on_value = FB_DISPLAY_ON_VALUE,\r
- //.standby_pin = FB_LCD_STANDBY_PIN,\r
- //.standby_value = FB_LCD_STANDBY_VALUE,\r
- //.mcu_fmk_pin = FB_MCU_FMK_PIN,\r
+ .disp_on_pin = FB_DISPLAY_ON_PIN,\r
+ .disp_on_value = FB_DISPLAY_ON_VALUE,\r
+ .standby_pin = FB_LCD_STANDBY_PIN,\r
+ .standby_value = FB_LCD_STANDBY_VALUE,\r
+ .mcu_fmk_pin = FB_MCU_FMK_PIN,\r
.lcd_info = &rk29_lcd_info,\r
.io_init = rk29_fb_io_init,\r
};\r
bool "RGB_HL070VM4AU"
config LCD_HSD070IDW1
bool "RGB Hannstar800x480"
+config LCD_HSD100PXN
+ bool "RGB Hannstar HSD100PXN(1024X768)"
config LCD_A060SE02
bool "MCU A060SE02"
config LCD_S1D13521
obj-$(CONFIG_HDMI_ANX7150) += hdmi_anx7150.o
obj-$(CONFIG_LCD_HX8357) += lcd_hx8357.o
+obj-$(CONFIG_LCD_HSD100PXN) += lcd_hsd100pxn.o
--- /dev/null
+#include <linux/fb.h>\r
+#include <linux/delay.h>\r
+#include "../../rk29_fb.h"\r
+#include <mach/gpio.h>\r
+#include <mach/iomux.h>\r
+#include <mach/board.h>\r
+#include "screen.h"\r
+\r
+\r
+/* Base */\r
+#define OUT_TYPE SCREEN_RGB\r
+#define OUT_FACE OUT_P888\r
+#define OUT_CLK 65\r
+#define LCDC_ACLK 150 //29 lcdc axi DMA ƵÂÊ\r
+\r
+/* Timing */\r
+#define H_PW 10\r
+#define H_BP 100\r
+#define H_VD 1024\r
+#define H_FP 210\r
+\r
+#define V_PW 10\r
+#define V_BP 10\r
+#define V_VD 768\r
+#define V_FP 18\r
+\r
+/* Other */\r
+#define DCLK_POL 0\r
+#define SWAP_RB 0\r
+\r
+\r
+void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )\r
+{\r
+ /* screen type & face */\r
+ screen->type = OUT_TYPE;\r
+ screen->face = OUT_FACE;\r
+\r
+ /* Screen size */\r
+ screen->x_res = H_VD;\r
+ screen->y_res = V_VD;\r
+\r
+ /* Timing */\r
+ screen->pixclock = OUT_CLK;\r
+ screen->left_margin = H_BP;\r
+ screen->right_margin = H_FP;\r
+ screen->hsync_len = H_PW;\r
+ screen->upper_margin = V_BP;\r
+ screen->lower_margin = V_FP;\r
+ screen->vsync_len = V_PW;\r
+\r
+ /* Pin polarity */\r
+ screen->pin_hsync = 0;\r
+ screen->pin_vsync = 0;\r
+ screen->pin_den = 0;\r
+ screen->pin_dclk = DCLK_POL;\r
+ screen->lcdc_aclk = LCDC_ACLK;\r
+\r
+ /* Swap rule */\r
+ screen->swap_rb = SWAP_RB;\r
+ screen->swap_rg = 0;\r
+ screen->swap_gb = 0;\r
+ screen->swap_delta = 0;\r
+ screen->swap_dumy = 0;\r
+\r
+ /* Operation function*/\r
+ screen->init = NULL;\r
+ screen->standby = NULL;\r
+}\r
+\r
+\r
+\r
u8 pin_vsync;
u8 pin_den;
u8 pin_dclk;
+ u8 lcdc_aclk;
u8 pin_dispon;
/* Swap rule */
#include "./display/screen/screen.h"
-
-#define CURSOR_BUF_SIZE 256 //rk29 cursor need 256B buf
-
#if 1
#define fbprintk(msg...) printk(msg);
#else
struct clk *dclk; //lcdc dclk
struct clk *dclk_parent; //lcdc dclk divider frequency source
struct clk *dclk_divider; //lcdc demodulator divider frequency
- struct clk *clk_share_mem; //lcdc share memory frequency
+ struct clk *aclk; //lcdc share memory frequency
+ struct clk *aclk_parent; //lcdc aclk divider frequency source
unsigned long dclk_rate;
/* lcdc reg base address and backup reg */
// set display_on
if(display_on != INVALID_GPIO)
- {
+ {
gpio_direction_output(display_on, 0);
gpio_set_value(display_on, enable ? display_on_pol : !display_on_pol);
}
gpio_direction_output(lcd_standby, 0);
gpio_set_value(lcd_standby, enable ? lcd_standby_pol : !lcd_standby_pol);
}
+
+ /********* open backlight just for test ***************/
+ rk29_mux_api_set(GPIO1B5_PWM0_NAME, 0);
+ if(0 != gpio_request(RK29_PIN1_PB5, NULL))
+ {
+ gpio_free(RK29_PIN1_PB5);
+ printk(">>>>>> RK29_PIN1_PB5 gpio_request err \n ");
+ }
+ gpio_direction_output(RK29_PIN1_PB5, GPIO_HIGH);
+ gpio_set_value(RK29_PIN1_PB5, GPIO_HIGH);
+ gpio_direction_output(RK29_PIN1_PB5, GPIO_HIGH);
+ printk("P1B5 High \n");
+/************************/
+
}
int mcu_do_refresh(struct rk29fb_inf *inf)
u16 x_res = screen->x_res, y_res = screen->y_res;
u32 clk_rate = 0;
u32 dclk_rate = 0;
+ u32 aclk_rate = 150000000;
+
+ if(!g_pdev) return -1;
fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__);
// let above to take effect
LcdWrReg(inf, REG_CFG_DONE, 0x01);
+ inf->clk = clk_get(&g_pdev->dev, "hclk_lcdc");
+ if (!inf->clk || IS_ERR(inf->clk))
+ {
+ printk(KERN_ERR "failed to get lcdc_hclk source\n");
+ return ;
+ }
+
+ inf->dclk = clk_get(&g_pdev->dev, "dclk_lcdc");
+ if (!inf->dclk || IS_ERR(inf->dclk))
+ {
+ printk(KERN_ERR "failed to get lcd dclock source\n");
+ return ;
+ }
+ inf->dclk_divider= clk_get(&g_pdev->dev, "dclk_lcdc_div");
+ if (!inf->dclk_divider || IS_ERR(inf->dclk_divider))
+ {
+ printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n");
+ return ;
+ }
+
+ if(inf->cur_screen == &inf->lcd_info) {
+ inf->dclk_parent = clk_get(&g_pdev->dev, "periph_pll");
+ } else {
+ inf->dclk_parent = clk_get(&g_pdev->dev, "codec_pll");
+ }
+
+ if (!inf->dclk_parent || IS_ERR(inf->dclk_parent))
+ {
+ printk(KERN_ERR "failed to get lcd dclock parent source\n");
+ return ;
+ }
+
+ inf->aclk = clk_get(&g_pdev->dev, "aclk_lcdc");
+ if (!inf->aclk || IS_ERR(inf->aclk))
+ {
+ printk(KERN_ERR "failed to get lcd clock clk_share_mem source \n");
+ return ;
+ }
+ inf->aclk_parent = clk_get(&g_pdev->dev, "periph_pll");
+ if (!inf->dclk_parent || IS_ERR(inf->dclk_parent))
+ {
+ printk(KERN_ERR "failed to get lcd dclock parent source\n");
+ return ;
+ }
+
// set lcdc clk
if(SCREEN_MCU==screen->type) screen->pixclock = 150; //mcu fix to 150 MHz
clk_set_parent(inf->dclk_divider, inf->dclk_parent);
clk_set_parent(inf->dclk, inf->dclk_divider);
+ clk_set_parent(inf->aclk, inf->aclk_parent);
dclk_rate = screen->pixclock * 1000000;
fbprintk(">>>>>> set lcdc dclk need %d HZ, clk_parent = %d hz \n ", screen->pixclock, clk_rate);
-#if 0
ret = clk_set_rate(inf->dclk_divider, dclk_rate);
-
if(ret)
{
printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n ");
}
+ if(screen->lcdc_aclk){
+ aclk_rate = screen->lcdc_aclk * 1000000;
+ }
+ ret = clk_set_rate(inf->aclk, aclk_rate);
+ if(ret){
+ printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n ");
+ }
clk_enable(inf->dclk);
clk_enable(inf->clk);
- clk_enable(inf->clk_share_mem);
-#endif
+ clk_enable(inf->aclk);
// init screen panel
if(screen->init && initscreen)
{
screen->init();
}
+
}
#ifdef CONFIG_CPU_FREQ
/*
struct fb_fix_screeninfo *fix = &info->fix;
struct rk29fb_screen *screen = inf->cur_screen;
-
u8 format = 0;
dma_addr_t map_dma;
u32 offset=0, addr=0, map_size=0, smem_len=0;
break;
}
- smem_len = fix->line_length * var->yres_virtual + CURSOR_BUF_SIZE; //cursor buf also alloc here
+ smem_len = fix->line_length * var->yres_virtual; //cursor buf also alloc here
map_size = PAGE_ALIGN(smem_len);
-
if (smem_len != fix->smem_len) // buffer need realloc
{
fbprintk(">>>>>> win1 buffer size is change(%d->%d)! remap memory!\n",fix->smem_len, smem_len);
addr = fix->smem_start + offset;
-
LcdMskReg(inf, SYS_CONFIG, m_W1_ENABLE|m_W1_FORMAT, v_W1_ENABLE(1)|v_W1_FORMAT(format));
xpos += (screen->left_margin + screen->hsync_len);
}
inf->preg = (LCDC_REG*)inf->reg_vir_base;
- if(0)
- {
- struct resource *rtc_mem = NULL;
- u32 rtc_reg_vir_base = NULL;
- rtc_mem = request_mem_region(RK29_RTC_PHYS, RK29_RTC_SIZE, NULL);
- rtc_reg_vir_base = (u32)ioremap(RK29_RTC_PHYS, RK29_RTC_SIZE);
- u32 rtc_reg = __raw_readl(rtc_reg_vir_base+0x04);
- __raw_writel( rtc_reg | 0x02, rtc_reg_vir_base+0x04 );
- rtc_reg = __raw_readl(rtc_reg_vir_base+0x04);
- }
-
-
/* Prepare win1 info */
fbprintk(">> Prepare win1 info \n");
inf->win1fb = framebuffer_alloc(sizeof(struct win1_par), &pdev->dev);
/* because after register_framebuffer, the win1fb_check_par and winfb_set_par execute immediately */
fbprintk(">> Init all lcdc and lcd before register_framebuffer \n");
init_lcdc(inf->win1fb);
-#if 0
- inf->clk = clk_get(&pdev->dev, "lcdc_hclk");
- if (!inf->clk || IS_ERR(inf->clk))
- {
- printk(KERN_ERR "failed to get lcdc_hclk source\n");
- ret = -ENOENT;
- goto unregister_win1fb;
- }
- inf->dclk = clk_get(&pdev->dev, "lcdc");
- if (!inf->dclk || IS_ERR(inf->dclk))
- {
- printk(KERN_ERR "failed to get lcd dclock source\n");
- ret = -ENOENT;
- goto unregister_win1fb;
- }
- inf->dclk_parent = clk_get(&pdev->dev, "arm_pll");
- if (!inf->dclk_parent || IS_ERR(inf->dclk_parent))
- {
- printk(KERN_ERR "failed to get lcd dclock parent source\n");
- ret = -ENOENT;
- goto unregister_win1fb;
- }
- inf->dclk_divider= clk_get(&pdev->dev, "lcdc_divider");
- if (!inf->dclk_divider || IS_ERR(inf->dclk_divider))
- {
- printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n");
- ret = -ENOENT;
- goto unregister_win1fb;
- }
-
- inf->clk_share_mem = clk_get(&pdev->dev, "lcdc_share_memory");
- if (!inf->clk_share_mem || IS_ERR(inf->clk_share_mem))
- {
- dev_err(&pdev->dev, "failed to get lcd clock clk_share_mem source \n");
- ret = -ENOENT;
- goto unregister_win1fb;
- }
#ifdef CONFIG_CPU_FREQ
- inf->freq_transition.notifier_call = rk29fb_freq_transition;
- cpufreq_register_notifier(&inf->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
+ // inf->freq_transition.notifier_call = rk29fb_freq_transition;
+ // cpufreq_register_notifier(&inf->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
#endif
fbprintk("got clock\n");
-#endif
if(mach_info)
{
mach_info->io_init(&fb_setting);
}
- //set_lcd_pin(pdev, 1);
+ set_lcd_pin(pdev, 1);
mdelay(10);
g_pdev = pdev;
inf->mcu_usetimer = 1;
projects / firefly-linux-kernel-4.4.55.git / commitdiff