--- /dev/null
+/* arch/arm/mach-rk29/board-rk29.c\r
+ *\r
+ * Copyright (C) 2010 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ */\r
+\r
+#include <linux/kernel.h>\r
+#include <linux/init.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/input.h>\r
+#include <linux/io.h>\r
+#include <linux/delay.h>\r
+#include <linux/i2c.h>\r
+#include <linux/spi/spi.h>\r
+#include <linux/mmc/host.h>\r
+#include <linux/android_pmem.h>\r
+#include <linux/usb/android_composite.h>\r
+\r
+#include <mach/hardware.h>\r
+#include <asm/setup.h>\r
+#include <asm/mach-types.h>\r
+#include <asm/mach/arch.h>\r
+#include <asm/mach/map.h>\r
+#include <asm/mach/flash.h>\r
+#include <asm/hardware/gic.h>\r
+\r
+#include <mach/iomux.h>\r
+#include <mach/gpio.h>\r
+#include <mach/irqs.h>\r
+#include <mach/rk29_iomap.h>\r
+#include <mach/board.h>\r
+#include <mach/rk29_nand.h>\r
+#include <mach/rk29_camera.h> /* ddl@rock-chips.com : camera support */\r
+#include <media/soc_camera.h> /* ddl@rock-chips.com : camera support */\r
+#include <mach/vpu_mem.h>\r
+\r
+#include <linux/regulator/rk29-pwm-regulator.h>\r
+#include <linux/regulator/machine.h>\r
+\r
+#include <linux/mtd/nand.h>\r
+#include <linux/mtd/partitions.h>\r
+\r
+#include "devices.h"\r
+#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"\r
+\r
+\r
+/* Set memory size of pmem */\r
+#ifdef CONFIG_MACH_RK29SDK_MEM_SIZE_M
+#define SDRAM_SIZE (CONFIG_MACH_RK29SDK_MEM_SIZE_M * SZ_1M)
+#else
+#define SDRAM_SIZE SZ_512M
+#endif
+#define PMEM_GPU_SIZE SZ_64M\r
+#define PMEM_UI_SIZE SZ_32M\r
+#define PMEM_VPU_SIZE SZ_32M\r
+#define PMEM_CAM_SIZE SZ_16M\r
+#define MEM_FB_SIZE (3*SZ_2M)\r
+\r
+#define PMEM_GPU_BASE ((u32)RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)\r
+#define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)\r
+#define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)\r
+#define PMEM_CAM_BASE (PMEM_VPU_BASE - PMEM_CAM_SIZE)\r
+#define MEM_FB_BASE (PMEM_CAM_BASE - MEM_FB_SIZE)\r
+#define LINUX_SIZE (MEM_FB_BASE - RK29_SDRAM_PHYS)\r
+\r
+extern struct sys_timer rk29_timer;\r
+\r
+#define NAND_CS_MAX_NUM 1 /*form 0 to 8, it is 0 when no nand flash */\r
+\r
+int rk29_nand_io_init(void)\r
+{\r
+#if (NAND_CS_MAX_NUM == 2)
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+#elif (NAND_CS_MAX_NUM == 3)
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+#elif (NAND_CS_MAX_NUM == 4)
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+ rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3);\r
+#elif (NAND_CS_MAX_NUM == 5) \r
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+ rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3);\r
+ rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); \r
+#elif (NAND_CS_MAX_NUM == 6)\r
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+ rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3);\r
+ rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); \r
+ rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); \r
+#elif (NAND_CS_MAX_NUM == 7)\r
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+ rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3);\r
+ rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); \r
+ rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); \r
+ rk29_mux_api_set(GPIO0D7_FLASHCSN6_NAME, GPIO0H_FLASH_CSN6); \r
+#elif (NAND_CS_MAX_NUM == 8)\r
+ rk29_mux_api_set(GPIO0D2_FLASHCSN1_NAME, GPIO0H_FLASH_CSN1);\r
+ rk29_mux_api_set(GPIO0D3_FLASHCSN2_NAME, GPIO0H_FLASH_CSN2);\r
+ rk29_mux_api_set(GPIO0D4_FLASHCSN3_NAME, GPIO0H_FLASH_CSN3);\r
+ rk29_mux_api_set(GPIO0D5_FLASHCSN4_NAME, GPIO0H_FLASH_CSN4); \r
+ rk29_mux_api_set(GPIO0D6_FLASHCSN5_NAME, GPIO0H_FLASH_CSN5); \r
+ rk29_mux_api_set(GPIO0D7_FLASHCSN6_NAME, GPIO0H_FLASH_CSN6); \r
+ rk29_mux_api_set(GPIO1A0_FLASHCS7_MDDRTQ_NAME, GPIO1L_FLASH_CS7); \r
+#endif\r
+ return 0;\r
+}\r
+\r
+struct rk29_nand_platform_data rk29_nand_data = {\r
+ .width = 1, /* data bus width in bytes */\r
+ .hw_ecc = 1, /* hw ecc 0: soft ecc */\r
+ .num_flash = 1,\r
+ .io_init = rk29_nand_io_init,\r
+};\r
+\r
+static struct rk29_gpio_bank rk29_gpiobankinit[] = {\r
+ {\r
+ .id = RK29_ID_GPIO0,\r
+ .offset = RK29_GPIO0_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO1,\r
+ .offset = RK29_GPIO1_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO2,\r
+ .offset = RK29_GPIO2_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO3,\r
+ .offset = RK29_GPIO3_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO4,\r
+ .offset = RK29_GPIO4_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO5,\r
+ .offset = RK29_GPIO5_BASE,\r
+ },\r
+ {\r
+ .id = RK29_ID_GPIO6,\r
+ .offset = RK29_GPIO6_BASE,\r
+ },\r
+};\r
+\r
+#ifdef CONFIG_FB_RK29\r
+/*****************************************************************************************\r
+ * lcd devices\r
+ * author: zyw@rock-chips.com\r
+ *****************************************************************************************/\r
+//#ifdef CONFIG_LCD_TD043MGEA1\r
+#define LCD_TXD_PIN INVALID_GPIO\r
+#define LCD_CLK_PIN INVALID_GPIO\r
+#define LCD_CS_PIN INVALID_GPIO\r
+/*****************************************************************************************\r
+* frame buffe devices\r
+* author: zyw@rock-chips.com\r
+*****************************************************************************************/\r
+#define FB_ID 0\r
+#define FB_DISPLAY_ON_PIN RK29_PIN6_PD0\r
+#define FB_LCD_STANDBY_PIN RK29_PIN6_PD1\r
+#define FB_LCD_CABC_EN_PIN RK29_PIN6_PD2\r
+#define FB_MCU_FMK_PIN INVALID_GPIO\r
+\r
+#define FB_DISPLAY_ON_VALUE GPIO_HIGH\r
+#define FB_LCD_STANDBY_VALUE GPIO_HIGH\r
+\r
+//#endif\r
+static int rk29_lcd_io_init(void)\r
+{\r
+ int ret = 0;\r
+ return ret;\r
+}\r
+\r
+static int rk29_lcd_io_deinit(void)\r
+{\r
+ int ret = 0;\r
+ return ret;\r
+}\r
+\r
+struct rk29lcd_info rk29_lcd_info = {\r
+ .txd_pin = LCD_TXD_PIN,\r
+ .clk_pin = LCD_CLK_PIN,\r
+ .cs_pin = LCD_CS_PIN,\r
+ .io_init = rk29_lcd_io_init,\r
+ .io_deinit = rk29_lcd_io_deinit,\r
+};\r
+\r
+\r
+static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)\r
+{\r
+ int ret = 0;\r
+ if(fb_setting->mcu_fmk_en && (FB_MCU_FMK_PIN != INVALID_GPIO))\r
+ {\r
+ ret = gpio_request(FB_MCU_FMK_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_MCU_FMK_PIN);\r
+ printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");\r
+ }\r
+ gpio_direction_input(FB_MCU_FMK_PIN);\r
+ }\r
+ if(fb_setting->disp_on_en && (FB_DISPLAY_ON_PIN != INVALID_GPIO))\r
+ {\r
+ ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_DISPLAY_ON_PIN);\r
+ printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");\r
+ }\r
+ }\r
+\r
+ if(fb_setting->disp_on_en && (FB_LCD_STANDBY_PIN != INVALID_GPIO))\r
+ {\r
+ ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_LCD_STANDBY_PIN);\r
+ printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");\r
+ }\r
+ }\r
+\r
+ if(FB_LCD_CABC_EN_PIN != INVALID_GPIO)\r
+ {\r
+ ret = gpio_request(FB_LCD_CABC_EN_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_LCD_CABC_EN_PIN);\r
+ printk(">>>>>> FB_LCD_CABC_EN_PIN gpio_request err \n ");\r
+ }\r
+ gpio_direction_output(FB_LCD_CABC_EN_PIN, 0);\r
+ gpio_set_value(FB_LCD_CABC_EN_PIN, GPIO_LOW);\r
+ }\r
+ \r
+ return ret;\r
+}\r
+\r
+struct rk29fb_info rk29_fb_info = {\r
+ .fb_id = FB_ID,\r
+ .disp_on_pin = FB_DISPLAY_ON_PIN,\r
+ .disp_on_value = FB_DISPLAY_ON_VALUE,\r
+ .standby_pin = FB_LCD_STANDBY_PIN,\r
+ .standby_value = FB_LCD_STANDBY_VALUE,\r
+ .mcu_fmk_pin = FB_MCU_FMK_PIN,\r
+ .lcd_info = &rk29_lcd_info,\r
+ .io_init = rk29_fb_io_init,\r
+};\r
+\r
+/* rk29 fb resource */\r
+struct resource rk29_fb_resource[] = {\r
+ [0] = {\r
+ .name = "lcdc reg",\r
+ .start = RK29_LCDC_PHYS,\r
+ .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,\r
+ .flags = IORESOURCE_MEM,\r
+ },\r
+ [1] = {\r
+ .name = "lcdc irq",\r
+ .start = IRQ_LCDC,\r
+ .end = IRQ_LCDC,\r
+ .flags = IORESOURCE_IRQ,\r
+ },\r
+ [2] = {\r
+ .name = "win1 buf",\r
+ .start = MEM_FB_BASE,\r
+ .end = MEM_FB_BASE + MEM_FB_SIZE,\r
+ .flags = IORESOURCE_MEM,\r
+ },\r
+};\r
+\r
+/*platform_device*/\r
+struct platform_device rk29_device_fb = {\r
+ .name = "rk29-fb",\r
+ .id = 4,\r
+ .num_resources = ARRAY_SIZE(rk29_fb_resource),\r
+ .resource = rk29_fb_resource,\r
+ .dev = {\r
+ .platform_data = &rk29_fb_info,\r
+ }\r
+};\r
+#endif\r
+\r
+static struct android_pmem_platform_data android_pmem_pdata = {\r
+ .name = "pmem",\r
+ .start = PMEM_UI_BASE,\r
+ .size = PMEM_UI_SIZE,\r
+ .no_allocator = 0,\r
+ .cached = 1,\r
+};\r
+\r
+static struct platform_device android_pmem_device = {\r
+ .name = "android_pmem",\r
+ .id = 0,\r
+ .dev = {\r
+ .platform_data = &android_pmem_pdata,\r
+ },\r
+};\r
+\r
+\r
+static struct android_pmem_platform_data android_pmem_cam_pdata = {\r
+ .name = "pmem_cam",\r
+ .start = PMEM_CAM_BASE,\r
+ .size = PMEM_CAM_SIZE,\r
+ .no_allocator = 0,\r
+ .cached = 1,\r
+};\r
+\r
+static struct platform_device android_pmem_cam_device = {\r
+ .name = "android_pmem",\r
+ .id = 1,\r
+ .dev = {\r
+ .platform_data = &android_pmem_cam_pdata,\r
+ },\r
+};\r
+\r
+\r
+static struct vpu_mem_platform_data vpu_mem_pdata = {\r
+ .name = "vpu_mem",\r
+ .start = PMEM_VPU_BASE,\r
+ .size = PMEM_VPU_SIZE,\r
+ .cached = 1,\r
+};\r
+\r
+static struct platform_device rk29_vpu_mem_device = {\r
+ .name = "vpu_mem",\r
+ .id = 2,\r
+ .dev = {\r
+ .platform_data = &vpu_mem_pdata,\r
+ },\r
+};\r
+\r
+\r
+/*HANNSTAR_P1003 touch*/\r
+#if defined (CONFIG_HANNSTAR_P1003)\r
+#define TOUCH_RESET_PIN RK29_PIN6_PC3\r
+#define TOUCH_INT_PIN RK29_PIN0_PA2\r
+\r
+int p1003_init_platform_hw(void)\r
+{\r
+ if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){\r
+ gpio_free(TOUCH_RESET_PIN);\r
+ printk("p1003_init_platform_hw gpio_request error\n");\r
+ return -EIO;\r
+ }\r
+\r
+ if(gpio_request(TOUCH_INT_PIN,NULL) != 0){\r
+ gpio_free(TOUCH_INT_PIN);\r
+ printk("p1003_init_platform_hw gpio_request error\n");\r
+ return -EIO;\r
+ }\r
+ gpio_pull_updown(TOUCH_INT_PIN, 1);\r
+ gpio_direction_output(TOUCH_RESET_PIN, 0);\r
+ mdelay(500);\r
+ gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);\r
+ mdelay(500);\r
+ gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+struct p1003_platform_data p1003_info = {\r
+ .model= 1003,\r
+ .init_platform_hw= p1003_init_platform_hw,\r
+\r
+};\r
+#endif\r
+\r
+\r
+/*****************************************************************************************\r
+ * i2c devices\r
+ * author: kfx@rock-chips.com\r
+*****************************************************************************************/\r
+static int rk29_i2c0_io_init(void)\r
+{\r
+ rk29_mux_api_set(GPIO2B7_I2C0SCL_NAME, GPIO2L_I2C0_SCL);\r
+ rk29_mux_api_set(GPIO2B6_I2C0SDA_NAME, GPIO2L_I2C0_SDA);\r
+ return 0;\r
+}\r
+\r
+static int rk29_i2c1_io_init(void)\r
+{\r
+ rk29_mux_api_set(GPIO1A7_I2C1SCL_NAME, GPIO1L_I2C1_SCL);\r
+ rk29_mux_api_set(GPIO1A6_I2C1SDA_NAME, GPIO1L_I2C1_SDA);\r
+ return 0;\r
+}\r
+static int rk29_i2c2_io_init(void)\r
+{\r
+ rk29_mux_api_set(GPIO5D4_I2C2SCL_NAME, GPIO5H_I2C2_SCL);\r
+ rk29_mux_api_set(GPIO5D3_I2C2SDA_NAME, GPIO5H_I2C2_SDA);\r
+ return 0;\r
+}\r
+\r
+static int rk29_i2c3_io_init(void)\r
+{\r
+ rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_I2C3_SCL);\r
+ rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_I2C3_SDA);\r
+ return 0;\r
+}\r
+\r
+struct rk29_i2c_platform_data default_i2c0_data = {\r
+ .bus_num = 0,\r
+ .flags = 0,\r
+ .slave_addr = 0xff,\r
+ .scl_rate = 400*1000,\r
+ .mode = I2C_MODE_IRQ,\r
+ .io_init = rk29_i2c0_io_init,\r
+};\r
+\r
+struct rk29_i2c_platform_data default_i2c1_data = {\r
+ .bus_num = 1,\r
+ .flags = 0,\r
+ .slave_addr = 0xff,\r
+ .scl_rate = 400*1000,\r
+ .mode = I2C_MODE_POLL,\r
+ .io_init = rk29_i2c1_io_init,\r
+};\r
+\r
+struct rk29_i2c_platform_data default_i2c2_data = {\r
+ .bus_num = 2,\r
+ .flags = 0,\r
+ .slave_addr = 0xff,\r
+ .scl_rate = 400*1000,\r
+ .mode = I2C_MODE_IRQ,\r
+ .io_init = rk29_i2c2_io_init,\r
+};\r
+\r
+struct rk29_i2c_platform_data default_i2c3_data = {\r
+ .bus_num = 3,\r
+ .flags = 0,\r
+ .slave_addr = 0xff,\r
+ .scl_rate = 400*1000,\r
+ .mode = I2C_MODE_POLL,\r
+ .io_init = rk29_i2c3_io_init,\r
+};\r
+\r
+#ifdef CONFIG_I2C0_RK29\r
+static struct i2c_board_info __initdata board_i2c0_devices[] = {\r
+#if defined (CONFIG_RK1000_CONTROL)\r
+ {\r
+ .type = "rk1000_control",\r
+ .addr = 0x40,\r
+ .flags = 0,\r
+ },\r
+#endif\r
+#if defined (CONFIG_SND_SOC_RK1000)\r
+ {\r
+ .type = "rk1000_i2c_codec",\r
+ .addr = 0x60,\r
+ .flags = 0,\r
+ },\r
+#endif\r
+#if defined (CONFIG_SND_SOC_WM8900)\r
+ {\r
+ .type = "wm8900",\r
+ .addr = 0x1A,\r
+ .flags = 0,\r
+ },\r
+#endif\r
+#if defined (CONFIG_BATTERY_STC3100)\r
+ {\r
+ .type = "stc3100",\r
+ .addr = 0x70,\r
+ .flags = 0,\r
+ }, \r
+#endif\r
+#if defined (CONFIG_BATTERY_BQ27510)\r
+ {\r
+ .type = "bq27510",\r
+ .addr = 0x55,\r
+ .flags = 0,\r
+ },\r
+#endif\r
+#if defined (CONFIG_RTC_HYM8563)\r
+ {\r
+ .type = "rtc_hym8563",\r
+ .addr = 0x51,\r
+ .flags = 0,\r
+ ///.irq = RK2818_PIN_PA4,\r
+ },\r
+#endif\r
+};\r
+#endif\r
+\r
+#ifdef CONFIG_I2C1_RK29\r
+static struct i2c_board_info __initdata board_i2c1_devices[] = {\r
+#if defined (CONFIG_RK1000_CONTROL1)\r
+ {\r
+ .type = "rk1000_control",\r
+ .addr = 0x40,\r
+ .flags = 0,\r
+ },\r
+#endif\r
+#if defined (CONFIG_SENSORS_AK8973)\r
+ {\r
+ .type = "ak8973",\r
+ .addr = 0x1c,\r
+ .flags = 0,\r
+ .irq = RK29_PIN4_PA1,\r
+ },\r
+#endif\r
+#if defined (CONFIG_SENSORS_AK8975)\r
+ {\r
+ .type = "ak8975",\r
+ .addr = 0x1c,\r
+ .flags = 0,\r
+ .irq = RK29_PIN4_PA1,\r
+ },\r
+#endif\r
+};\r
+#endif\r
+\r
+#ifdef CONFIG_I2C2_RK29\r
+static struct i2c_board_info __initdata board_i2c2_devices[] = {\r
+#if defined (CONFIG_HANNSTAR_P1003)\r
+ {\r
+ .type = "p1003_touch",\r
+ .addr = 0x04,\r
+ .flags = 0,\r
+ .irq = RK29_PIN0_PA2,\r
+ .platform_data = &p1003_info,\r
+ },\r
+#endif\r
+};\r
+#endif\r
+\r
+#ifdef CONFIG_I2C3_RK29\r
+static struct i2c_board_info __initdata board_i2c3_devices[] = {\r
+};\r
+#endif\r
+\r
+/*****************************************************************************************\r
+ * camera devices\r
+ * author: ddl@rock-chips.com\r
+ *****************************************************************************************/\r
+#ifdef CONFIG_VIDEO_RK29\r
+#define SENSOR_NAME_0 RK29_CAM_SENSOR_NAME_OV5642 /* back camera sensor */\r
+#define SENSOR_IIC_ADDR_0 0x78\r
+#define SENSOR_IIC_ADAPTER_ID_0 1\r
+#define SENSOR_POWER_PIN_0 RK29_PIN6_PB7\r
+#define SENSOR_RESET_PIN_0 INVALID_GPIO\r
+#define SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L\r
+#define SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L\r
+\r
+\r
+#define SENSOR_NAME_1 RK29_CAM_SENSOR_NAME_OV2659 /* front camera sensor */\r
+#define SENSOR_IIC_ADDR_1 0x60\r
+#define SENSOR_IIC_ADAPTER_ID_1 1\r
+#define SENSOR_POWER_PIN_1 RK29_PIN5_PD7\r
+#define SENSOR_RESET_PIN_1 INVALID_GPIO\r
+#define SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L\r
+#define SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L\r
+\r
+static int rk29_sensor_io_init(void);\r
+static int rk29_sensor_io_deinit(void);\r
+\r
+struct rk29camera_platform_data rk29_camera_platform_data = {\r
+ .io_init = rk29_sensor_io_init,\r
+ .io_deinit = rk29_sensor_io_deinit,\r
+ .gpio_res = {\r
+ {\r
+ .gpio_reset = SENSOR_RESET_PIN_0,\r
+ .gpio_power = SENSOR_POWER_PIN_0,\r
+ .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_0|SENSOR_RESETACTIVE_LEVEL_0),\r
+ .dev_name = SENSOR_NAME_0,\r
+ }, {\r
+ .gpio_reset = SENSOR_RESET_PIN_1,\r
+ .gpio_power = SENSOR_POWER_PIN_1,\r
+ .gpio_flag = (SENSOR_POWERACTIVE_LEVEL_1|SENSOR_RESETACTIVE_LEVEL_1),\r
+ .dev_name = SENSOR_NAME_1,\r
+ }\r
+ }\r
+};\r
+\r
+static int rk29_sensor_io_init(void)\r
+{\r
+ int ret = 0, i;\r
+ unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;\r
+ unsigned int camera_ioflag;\r
+\r
+ for (i=0; i<2; i++) {\r
+ camera_reset = rk29_camera_platform_data.gpio_res[i].gpio_reset;\r
+ camera_power = rk29_camera_platform_data.gpio_res[i].gpio_power;\r
+ camera_ioflag = rk29_camera_platform_data.gpio_res[i].gpio_flag;\r
+\r
+ if (camera_power != INVALID_GPIO) {\r
+ ret = gpio_request(camera_power, "camera power");\r
+ if (ret)\r
+ continue;\r
+\r
+ gpio_set_value(camera_reset, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+ gpio_direction_output(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+\r
+ //printk("\n%s....%d %x \n",__FUNCTION__,__LINE__,(((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+\r
+ }\r
+\r
+ if (camera_reset != INVALID_GPIO) {\r
+ ret = gpio_request(camera_reset, "camera reset");\r
+ if (ret) {\r
+ if (camera_power != INVALID_GPIO)\r
+ gpio_free(camera_power);\r
+\r
+ continue;\r
+ }\r
+\r
+ gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+ gpio_direction_output(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+\r
+ //printk("\n%s....%d %x \n",__FUNCTION__,__LINE__,((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static int rk29_sensor_io_deinit(void)\r
+{\r
+ unsigned int i;\r
+ unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;\r
+\r
+ //printk("\n%s....%d ******** ddl *********\n",__FUNCTION__,__LINE__);\r
+\r
+ for (i=0; i<2; i++) {\r
+ camera_reset = rk29_camera_platform_data.gpio_res[i].gpio_reset;\r
+ camera_power = rk29_camera_platform_data.gpio_res[i].gpio_power;\r
+\r
+ if (camera_power != INVALID_GPIO){\r
+ gpio_direction_input(camera_power);\r
+ gpio_free(camera_power);\r
+ }\r
+\r
+ if (camera_reset != INVALID_GPIO) {\r
+ gpio_direction_input(camera_reset);\r
+ gpio_free(camera_reset);\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+static int rk29_sensor_power(struct device *dev, int on)\r
+{\r
+ unsigned int camera_reset = INVALID_GPIO, camera_power = INVALID_GPIO;\r
+ unsigned int camera_ioflag;\r
+\r
+ if(rk29_camera_platform_data.gpio_res[0].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[0].dev_name, dev_name(dev)) == 0)) {\r
+ camera_reset = rk29_camera_platform_data.gpio_res[0].gpio_reset;\r
+ camera_power = rk29_camera_platform_data.gpio_res[0].gpio_power;\r
+ camera_ioflag = rk29_camera_platform_data.gpio_res[0].gpio_flag;\r
+ } else if (rk29_camera_platform_data.gpio_res[1].dev_name && (strcmp(rk29_camera_platform_data.gpio_res[1].dev_name, dev_name(dev)) == 0)) {\r
+ camera_reset = rk29_camera_platform_data.gpio_res[1].gpio_reset;\r
+ camera_power = rk29_camera_platform_data.gpio_res[1].gpio_power;\r
+ camera_ioflag = rk29_camera_platform_data.gpio_res[1].gpio_flag;\r
+ }\r
+\r
+ if (camera_reset != INVALID_GPIO) {\r
+ gpio_set_value(camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+ //printk("\n%s..%s..ResetPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev),camera_reset, ((camera_ioflag&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+ }\r
+ if (camera_power != INVALID_GPIO) {\r
+ if (on) {\r
+ gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+ //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+ } else {\r
+ gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+ //printk("\n%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));\r
+ }\r
+ }\r
+\r
+ if (camera_reset != INVALID_GPIO) {\r
+ if (on) {\r
+ msleep(3); /* delay 3 ms */\r
+ gpio_set_value(camera_reset,(((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+ //printk("\n%s..%s..ResetPin= %d..PinLevel = %x \n",__FUNCTION__,dev_name(dev), camera_reset, (((~camera_ioflag)&RK29_CAM_RESETACTIVE_MASK)>>RK29_CAM_RESETACTIVE_BITPOS));\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+static struct i2c_board_info rk29_i2c_cam_info_0[] = {\r
+ {\r
+ I2C_BOARD_INFO(SENSOR_NAME_0, SENSOR_IIC_ADDR_0>>1)\r
+ },\r
+};\r
+\r
+struct soc_camera_link rk29_iclink_0 = {\r
+ .bus_id = RK29_CAM_PLATFORM_DEV_ID,\r
+ .power = rk29_sensor_power,\r
+ .board_info = &rk29_i2c_cam_info_0[0],\r
+ .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_0,\r
+ .module_name = SENSOR_NAME_0,\r
+};\r
+\r
+/*platform_device : soc-camera need */\r
+struct platform_device rk29_soc_camera_pdrv_0 = {\r
+ .name = "soc-camera-pdrv",\r
+ .id = 0,\r
+ .dev = {\r
+ .init_name = SENSOR_NAME_0,\r
+ .platform_data = &rk29_iclink_0,\r
+ },\r
+};\r
+\r
+static struct i2c_board_info rk29_i2c_cam_info_1[] = {\r
+ {\r
+ I2C_BOARD_INFO(SENSOR_NAME_1, SENSOR_IIC_ADDR_1>>1)\r
+ },\r
+};\r
+\r
+struct soc_camera_link rk29_iclink_1 = {\r
+ .bus_id = RK29_CAM_PLATFORM_DEV_ID,\r
+ .power = rk29_sensor_power,\r
+ .board_info = &rk29_i2c_cam_info_1[0],\r
+ .i2c_adapter_id = SENSOR_IIC_ADAPTER_ID_1,\r
+ .module_name = SENSOR_NAME_1,\r
+};\r
+\r
+/*platform_device : soc-camera need */\r
+struct platform_device rk29_soc_camera_pdrv_1 = {\r
+ .name = "soc-camera-pdrv",\r
+ .id = 1,\r
+ .dev = {\r
+ .init_name = SENSOR_NAME_1,\r
+ .platform_data = &rk29_iclink_1,\r
+ },\r
+};\r
+\r
+\r
+extern struct platform_device rk29_device_camera;\r
+#endif\r
+/*****************************************************************************************\r
+ * backlight devices\r
+ * author: nzy@rock-chips.com\r
+ *****************************************************************************************/\r
+#ifdef CONFIG_BACKLIGHT_RK29_BL\r
+ /*\r
+ GPIO1B5_PWM0_NAME, GPIO1L_PWM0\r
+ GPIO5D2_PWM1_UART1SIRIN_NAME, GPIO5H_PWM1\r
+ GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME, GPIO2L_PWM2\r
+ GPIO1A5_EMMCPWREN_PWM3_NAME, GPIO1L_PWM3\r
+ */\r
+\r
+#define PWM_ID 0\r
+#define PWM_MUX_NAME GPIO1B5_PWM0_NAME\r
+#define PWM_MUX_MODE GPIO1L_PWM0\r
+#define PWM_MUX_MODE_GPIO GPIO1L_GPIO1B5\r
+#define PWM_EFFECT_VALUE 1\r
+\r
+//#define LCD_DISP_ON_PIN\r
+\r
+#ifdef LCD_DISP_ON_PIN\r
+#define BL_EN_MUX_NAME GPIOF34_UART3_SEL_NAME\r
+#define BL_EN_MUX_MODE IOMUXB_GPIO1_B34\r
+\r
+#define BL_EN_PIN GPIO0L_GPIO0A5\r
+#define BL_EN_VALUE GPIO_HIGH\r
+#endif\r
+static int rk29_backlight_io_init(void)\r
+{\r
+ int ret = 0;\r
+\r
+ rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);\r
+ #ifdef LCD_DISP_ON_PIN\r
+ rk29_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);\r
+\r
+ ret = gpio_request(BL_EN_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(BL_EN_PIN);\r
+ }\r
+\r
+ gpio_direction_output(BL_EN_PIN, 0);\r
+ gpio_set_value(BL_EN_PIN, BL_EN_VALUE);\r
+ #endif\r
+ return ret;\r
+}\r
+\r
+static int rk29_backlight_io_deinit(void)\r
+{\r
+ int ret = 0;\r
+ #ifdef LCD_DISP_ON_PIN\r
+ gpio_free(BL_EN_PIN);\r
+ #endif\r
+ rk29_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);\r
+ return ret;\r
+}\r
+struct rk29_bl_info rk29_bl_info = {\r
+ .pwm_id = PWM_ID,\r
+ .bl_ref = PWM_EFFECT_VALUE,\r
+ .io_init = rk29_backlight_io_init,\r
+ .io_deinit = rk29_backlight_io_deinit,\r
+};\r
+#endif\r
+\r
+/*****************************************************************************************\r
+* pwm voltage regulator devices\r
+******************************************************************************************/\r
+#if defined (CONFIG_RK29_PWM_REGULATOR)\r
+\r
+#define REGULATOR_PWM_ID 2\r
+#define REGULATOR_PWM_MUX_NAME GPIO2A3_SDMMC0WRITEPRT_PWM2_NAME\r
+#define REGULATOR_PWM_MUX_MODE GPIO2L_PWM2\r
+#define REGULATOR_PWM_MUX_MODE_GPIO GPIO2L_GPIO2A3\r
+#define REGULATOR_PWM_GPIO RK29_PIN2_PA3\r
+\r
+static struct regulator_consumer_supply pwm_consumers[] = {\r
+ {
+ .supply = "vcore",\r
+ }
+};
+
+static struct regulator_init_data rk29_pwm_regulator_data = {\r
+ .constraints = {
+ .name = "PWM2",\r
+ .min_uV = 1200000,
+ .max_uV = 1400000,\r
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(pwm_consumers),\r
+ .consumer_supplies = pwm_consumers,\r
+};\r
+\r
+static struct pwm_platform_data rk29_regulator_pwm_platform_data = {\r
+ .pwm_id = REGULATOR_PWM_ID,\r
+ .pwm_gpio = REGULATOR_PWM_GPIO,\r
+ //.pwm_iomux_name[] = REGULATOR_PWM_MUX_NAME;\r
+ .pwm_iomux_name = REGULATOR_PWM_MUX_NAME,\r
+ .pwm_iomux_pwm = REGULATOR_PWM_MUX_MODE,\r
+ .pwm_iomux_gpio = REGULATOR_PWM_MUX_MODE_GPIO,\r
+ .init_data = &rk29_pwm_regulator_data,\r
+};\r
+\r
+static struct platform_device rk29_device_pwm_regulator = {\r
+ .name = "pwm-voltage-regulator",\r
+ .id = -1,
+ .dev = {
+ .platform_data = &rk29_regulator_pwm_platform_data,\r
+ },
+};\r
+\r
+#endif\r
+\r
+/*****************************************************************************************\r
+ * SDMMC devices\r
+*****************************************************************************************/\r
+#ifdef CONFIG_SDMMC0_RK29\r
+static int rk29_sdmmc0_cfg_gpio(void)\r
+{\r
+ rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);\r
+ rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);\r
+ rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);\r
+ rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);\r
+ rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);\r
+ rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);\r
+ rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N); \r
+ rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5); ///GPIO5H_SDMMC0_PWR_EN); ///GPIO5H_GPIO5D5);\r
+ gpio_request(RK29_PIN5_PD5,"sdmmc");\r
+ gpio_set_value(RK29_PIN5_PD5,GPIO_HIGH);\r
+ mdelay(100);\r
+ gpio_set_value(RK29_PIN5_PD5,GPIO_LOW);\r
+ return 0;\r
+}\r
+\r
+#define CONFIG_SDMMC0_USE_DMA\r
+struct rk29_sdmmc_platform_data default_sdmmc0_data = {\r
+ .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|\r
+ MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|\r
+ MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),\r
+ .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),\r
+ .io_init = rk29_sdmmc0_cfg_gpio,\r
+ .dma_name = "sd_mmc",\r
+#ifdef CONFIG_SDMMC0_USE_DMA\r
+ .use_dma = 1,\r
+#else\r
+ .use_dma = 0,\r
+#endif\r
+};\r
+#endif\r
+#ifdef CONFIG_SDMMC1_RK29\r
+#define CONFIG_SDMMC1_USE_DMA\r
+static int rk29_sdmmc1_cfg_gpio(void)\r
+{\r
+ rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);\r
+ rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);\r
+ rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);\r
+ rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);\r
+ rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);\r
+ rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);\r
+ //rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_SDMMC1_DETECT_N);\r
+ return 0;\r
+}\r
+
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+static int rk29sdk_wifi_status(struct device *dev);
+static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);\r
+#endif
+
+#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK29_PIN1_PD6
+
+struct rk29_sdmmc_platform_data default_sdmmc1_data = {\r
+ .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|\r
+ MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|\r
+ MMC_VDD_32_33|MMC_VDD_33_34),\r
+ .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|\r
+ MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),\r
+ .io_init = rk29_sdmmc1_cfg_gpio,\r
+ .dma_name = "sdio",\r
+#ifdef CONFIG_SDMMC1_USE_DMA\r
+ .use_dma = 1,\r
+#else\r
+ .use_dma = 0,\r
+#endif\r
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ .status = rk29sdk_wifi_status,
+ .register_status_notify = rk29sdk_wifi_status_register,
+#endif
+#if 0
+ .detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
+#endif
+};\r
+#endif\r
+
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+#define RK29SDK_WIFI_BT_GPIO_POWER_N RK29_PIN5_PD6
+#define RK29SDK_WIFI_GPIO_RESET_N RK29_PIN6_PC0
+#define RK29SDK_BT_GPIO_RESET_N RK29_PIN6_PC4
+
+static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+int rk29sdk_wifi_power_state = 0;
+int rk29sdk_bt_power_state = 0;
+
+static int rk29sdk_wifi_status(struct device *dev)
+{
+ return rk29sdk_wifi_cd;
+}
+
+static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
+{
+ if(wifi_status_cb)
+ return -EAGAIN;
+ wifi_status_cb = callback;
+ wifi_status_cb_devid = dev_id;
+ return 0;
+}
+
+static int rk29sdk_wifi_bt_gpio_control_init(void)
+{
+ if (gpio_request(RK29SDK_WIFI_BT_GPIO_POWER_N, "wifi_bt_power")) {
+ pr_info("%s: request wifi_bt power gpio failed\n", __func__);
+ return -1;
+ }
+
+ if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
+ pr_info("%s: request wifi reset gpio failed\n", __func__);
+ gpio_free(RK29SDK_WIFI_BT_GPIO_POWER_N);
+ return -1;
+ }
+
+ if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
+ pr_info("%s: request bt reset gpio failed\n", __func__);
+ gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
+ return -1;
+ }
+
+ gpio_direction_output(RK29SDK_WIFI_BT_GPIO_POWER_N, GPIO_LOW);
+ gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
+ gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
+
+ pr_info("%s: init finished\n",__func__);
+
+ return 0;
+}
+
+static int rk29sdk_wifi_power(int on)
+{
+ pr_info("%s: %d\n", __func__, on);
+ if (on){
+ gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, on);
+ mdelay(100);
+ pr_info("wifi turn on power\n");
+ }else{
+ if (!rk29sdk_bt_power_state){
+ gpio_set_value(RK29SDK_WIFI_BT_GPIO_POWER_N, on);
+ mdelay(100);
+ pr_info("wifi shut off power\n");
+ }else
+ {
+ pr_info("wifi shouldn't shut off power, bt is using it!\n");
+ }
+
+ }
+
+ rk29sdk_wifi_power_state = on;
+ return 0;
+}
+
+static int rk29sdk_wifi_reset_state;
+static int rk29sdk_wifi_reset(int on)
+{
+ pr_info("%s: %d\n", __func__, on);
+ gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
+ mdelay(100);
+ rk29sdk_wifi_reset_state = on;
+ return 0;
+}
+
+static int rk29sdk_wifi_set_carddetect(int val)
+{
+ pr_info("%s:%d\n", __func__, val);
+ rk29sdk_wifi_cd = val;
+ if (wifi_status_cb){
+ wifi_status_cb(val, wifi_status_cb_devid);
+ }else {
+ pr_warning("%s, nobody to notify\n", __func__);
+ }
+ return 0;
+}
+
+static struct wifi_platform_data rk29sdk_wifi_control = {
+ .set_power = rk29sdk_wifi_power,
+ .set_reset = rk29sdk_wifi_reset,
+ .set_carddetect = rk29sdk_wifi_set_carddetect,
+};
+static struct platform_device rk29sdk_wifi_device = {
+ .name = "bcm4329_wlan",
+ .id = 1,
+ .dev = {
+ .platform_data = &rk29sdk_wifi_control,
+ },
+};
+#endif
+
+#ifdef CONFIG_VIVANTE\r
+static struct resource resources_gpu[] = {\r
+ [0] = {\r
+ .name = "gpu_irq",\r
+ .start = IRQ_GPU,\r
+ .end = IRQ_GPU,\r
+ .flags = IORESOURCE_IRQ,\r
+ },\r
+ [1] = {\r
+ .name = "gpu_base",\r
+ .start = RK29_GPU_PHYS,\r
+ .end = RK29_GPU_PHYS + RK29_GPU_PHYS_SIZE,\r
+ .flags = IORESOURCE_MEM,\r
+ },\r
+ [2] = {\r
+ .name = "gpu_mem",\r
+ .start = PMEM_GPU_BASE,\r
+ .end = PMEM_GPU_BASE + PMEM_GPU_SIZE,\r
+ .flags = IORESOURCE_MEM,\r
+ },\r
+};\r
+struct platform_device rk29_device_gpu = {\r
+ .name = "galcore",\r
+ .id = 0,\r
+ .num_resources = ARRAY_SIZE(resources_gpu),\r
+ .resource = resources_gpu,\r
+};\r
+#endif\r
+#ifdef CONFIG_KEYS_RK29\r
+extern struct rk29_keys_platform_data rk29_keys_pdata;\r
+static struct platform_device rk29_device_keys = {\r
+ .name = "rk29-keypad",\r
+ .id = -1,\r
+ .dev = {\r
+ .platform_data = &rk29_keys_pdata,\r
+ },\r
+};\r
+#endif\r
+/********************usb*********************/\r
+struct usb_mass_storage_platform_data mass_storage_pdata = {\r
+ .nluns = 1,\r
+ .vendor = "RockChip",\r
+ .product = "rk9 sdk",\r
+ .release = 0x0100,\r
+};\r
+\r
+static void __init rk29_board_iomux_init(void)\r
+{\r
+ #ifdef CONFIG_UART0_RK29\r
+ rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);\r
+ rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);\r
+ #ifdef CONFIG_UART0_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);\r
+ rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);\r
+ #endif\r
+ #endif\r
+ #ifdef CONFIG_UART1_RK29\r
+ rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);\r
+ rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);\r
+ #endif\r
+ #ifdef CONFIG_UART2_RK29\r
+ rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);\r
+ rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);\r
+ #ifdef CONFIG_UART2_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);\r
+ rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);\r
+ #endif\r
+ #endif\r
+ #ifdef CONFIG_UART3_RK29\r
+ rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);\r
+ rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);\r
+ #ifdef CONFIG_UART3_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);\r
+ rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);\r
+ #endif\r
+ #endif\r
+ #ifdef CONFIG_SPIM0_RK29\r
+ rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME, GPIO2H_SPI0_CLK);\r
+ rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME, GPIO2H_SPI0_CSN0);\r
+ rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME, GPIO2H_SPI0_TXD);\r
+ rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME, GPIO2H_SPI0_RXD);\r
+ #endif\r
+ #ifdef CONFIG_SPIM1_RK29\r
+ rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);\r
+ rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME, GPIO2H_SPI1_CSN0);\r
+ rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME, GPIO2H_SPI1_TXD);\r
+ rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME, GPIO2H_SPI1_RXD);\r
+ #endif\r
+ #ifdef CONFIG_RK29_VMAC\r
+ rk29_mux_api_set(GPIO4C0_RMIICLKOUT_RMIICLKIN_NAME, GPIO4H_RMII_CLKOUT);\r
+ rk29_mux_api_set(GPIO4C1_RMIITXEN_MIITXEN_NAME, GPIO4H_RMII_TX_EN);\r
+ rk29_mux_api_set(GPIO4C2_RMIITXD1_MIITXD1_NAME, GPIO4H_RMII_TXD1);\r
+ rk29_mux_api_set(GPIO4C3_RMIITXD0_MIITXD0_NAME, GPIO4H_RMII_TXD0);\r
+ rk29_mux_api_set(GPIO4C4_RMIIRXERR_MIIRXERR_NAME, GPIO4H_RMII_RX_ERR);\r
+ rk29_mux_api_set(GPIO4C5_RMIICSRDVALID_MIIRXDVALID_NAME, GPIO4H_RMII_CSR_DVALID);\r
+ rk29_mux_api_set(GPIO4C6_RMIIRXD1_MIIRXD1_NAME, GPIO4H_RMII_RXD1);\r
+ rk29_mux_api_set(GPIO4C7_RMIIRXD0_MIIRXD0_NAME, GPIO4H_RMII_RXD0);\r
+\r
+ rk29_mux_api_set(GPIO0A7_MIIMDCLK_NAME, GPIO0L_MII_MDCLK);\r
+ rk29_mux_api_set(GPIO0A6_MIIMD_NAME, GPIO0L_MII_MD);\r
+ #endif\r
+ #ifdef CONFIG_RK29_PWM_REGULATOR\r
+ rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);\r
+ #endif\r
+}\r
+\r
+static struct platform_device *devices[] __initdata = {\r
+#ifdef CONFIG_UART1_RK29\r
+ &rk29_device_uart1,\r
+#endif\r
+#ifdef CONFIG_RK29_PWM_REGULATOR\r
+ &rk29_device_pwm_regulator,\r
+#endif\r
+#ifdef CONFIG_SPIM0_RK29\r
+ &rk29xx_device_spi0m,\r
+#endif\r
+#ifdef CONFIG_SPIM1_RK29\r
+ &rk29xx_device_spi1m,\r
+#endif\r
+#ifdef CONFIG_ADC_RK29\r
+ &rk29_device_adc,\r
+#endif\r
+#ifdef CONFIG_I2C0_RK29\r
+ &rk29_device_i2c0,\r
+#endif\r
+#ifdef CONFIG_I2C1_RK29\r
+ &rk29_device_i2c1,\r
+#endif\r
+#ifdef CONFIG_I2C2_RK29\r
+ &rk29_device_i2c2,\r
+#endif\r
+#ifdef CONFIG_I2C3_RK29\r
+ &rk29_device_i2c3,\r
+#endif\r
+\r
+#ifdef CONFIG_SND_RK29_SOC_I2S_2CH\r
+ &rk29_device_iis_2ch,\r
+#endif\r
+#ifdef CONFIG_SND_RK29_SOC_I2S_8CH\r
+ &rk29_device_iis_8ch,\r
+#endif\r
+\r
+#ifdef CONFIG_KEYS_RK29\r
+ &rk29_device_keys,\r
+#endif\r
+#ifdef CONFIG_SDMMC0_RK29\r
+ &rk29_device_sdmmc0,\r
+#endif\r
+#ifdef CONFIG_SDMMC1_RK29\r
+ &rk29_device_sdmmc1,\r
+#endif\r
+\r
+#ifdef CONFIG_MTD_NAND_RK29XX\r
+ &rk29xx_device_nand,\r
+#endif\r
+\r
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ &rk29sdk_wifi_device,
+#endif
+#ifdef CONFIG_MTD_NAND_RK29\r
+ &rk29_device_nand,\r
+#endif\r
+\r
+#ifdef CONFIG_FB_RK29\r
+ &rk29_device_fb,\r
+#endif\r
+#ifdef CONFIG_BACKLIGHT_RK29_BL\r
+ &rk29_device_backlight,\r
+#endif\r
+#ifdef CONFIG_RK29_VMAC\r
+ &rk29_device_vmac,\r
+#endif\r
+#ifdef CONFIG_VIVANTE\r
+ &rk29_device_gpu,\r
+#endif\r
+#ifdef CONFIG_VIDEO_RK29\r
+ &rk29_device_camera, /* ddl@rock-chips.com : camera support */\r
+ &rk29_soc_camera_pdrv_0,\r
+ &rk29_soc_camera_pdrv_1,\r
+ &android_pmem_cam_device,\r
+#endif\r
+ &android_pmem_device,\r
+ &rk29_vpu_mem_device,\r
+#ifdef CONFIG_DWC_OTG\r
+ &rk29_device_dwc_otg,\r
+#endif\r
+#ifdef CONFIG_USB_ANDROID\r
+ &android_usb_device,\r
+ &usb_mass_storage_device,\r
+#endif\r
+};\r
+\r
+/*****************************************************************************************\r
+ * spi devices\r
+ * author: cmc@rock-chips.com\r
+ *****************************************************************************************/\r
+static int rk29_vmac_register_set(void)\r
+{\r
+ //config rk29 vmac as rmii, 100MHz \r
+ u32 value= readl(RK29_GRF_BASE + 0xbc);\r
+ value = (value & 0xfff7ff) | (0x400);\r
+ writel(value, RK29_GRF_BASE + 0xbc);\r
+ return 0;\r
+}\r
+\r
+static int rk29_rmii_io_init(void)\r
+{\r
+ int err;\r
+\r
+ //set dm9161 rmii\r
+ rk29_mux_api_set(GPIO2D3_I2S0SDI_MIICOL_NAME, GPIO2H_GPIO2D3);\r
+ err = gpio_request(RK29_PIN2_PD3, "rmii");\r
+ if (err) {\r
+ gpio_free(RK29_PIN2_PD3);\r
+ printk("-------request RK29_PIN2_PD3 fail--------\n");\r
+ return -1;\r
+ }\r
+ gpio_direction_output(RK29_PIN2_PD3, GPIO_HIGH);\r
+ gpio_set_value(RK29_PIN2_PD3, GPIO_HIGH);\r
+\r
+ //rmii power on\r
+ err = gpio_request(RK29_PIN6_PB0, "rmii_power_en");\r
+ if (err) {\r
+ gpio_free(RK29_PIN6_PB0);\r
+ gpio_free(RK29_PIN2_PD3);\r
+ printk("-------request RK29_PIN6_PB0 fail--------\n");\r
+ return -1;\r
+ } \r
+ gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);\r
+ gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);\r
+ \r
+ return 0;\r
+}\r
+\r
+static int rk29_rmii_power_control(int enable)\r
+{\r
+ if (enable) {\r
+ //set dm9161 as rmii\r
+ gpio_direction_output(RK29_PIN2_PD3, GPIO_HIGH);\r
+ gpio_set_value(RK29_PIN2_PD3, GPIO_HIGH);\r
+\r
+ //enable rmii power\r
+ gpio_direction_output(RK29_PIN6_PB0, GPIO_HIGH);\r
+ gpio_set_value(RK29_PIN6_PB0, GPIO_HIGH);\r
+ \r
+ }\r
+ else {\r
+ gpio_direction_output(RK29_PIN6_PB0, GPIO_LOW);\r
+ gpio_set_value(RK29_PIN6_PB0, GPIO_LOW);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+struct rk29_vmac_platform_data rk29_vmac_pdata = {\r
+ .vmac_register_set = rk29_vmac_register_set,\r
+ .rmii_io_init = rk29_rmii_io_init,\r
+ .rmii_power_control = rk29_rmii_power_control,\r
+};\r
+\r
+/*****************************************************************************************\r
+ * spi devices\r
+ * author: cmc@rock-chips.com\r
+ *****************************************************************************************/\r
+#define SPI_CHIPSELECT_NUM 2\r
+struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {\r
+ {\r
+ .name = "spi0 cs0",\r
+ .cs_gpio = RK29_PIN2_PC1,\r
+ .cs_iomux_name = NULL,\r
+ },\r
+ {\r
+ .name = "spi0 cs1",\r
+ .cs_gpio = RK29_PIN1_PA4,\r
+ .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL\r
+ .cs_iomux_mode = GPIO1L_SPI0_CSN1,\r
+ }\r
+};\r
+\r
+struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {\r
+ {\r
+ .name = "spi1 cs0",\r
+ .cs_gpio = RK29_PIN2_PC5,\r
+ .cs_iomux_name = NULL,\r
+ },\r
+ {\r
+ .name = "spi1 cs1",\r
+ .cs_gpio = RK29_PIN1_PA3,\r
+ .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL\r
+ .cs_iomux_mode = GPIO1L_SPI1_CSN1,\r
+ }\r
+};\r
+\r
+static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)\r
+{\r
+#if 1\r
+ int i,j,ret;\r
+\r
+ //cs\r
+ if (cs_gpios) {\r
+ for (i=0; i<cs_num; i++) {\r
+ rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);\r
+ ret = gpio_request(cs_gpios[i].cs_gpio, cs_gpios[i].name);\r
+ if (ret) {\r
+ for (j=0;j<i;j++) {\r
+ gpio_free(cs_gpios[j].cs_gpio);\r
+ //rk29_mux_api_mode_resume(cs_gpios[j].cs_iomux_name);\r
+ }\r
+ printk("[fun:%s, line:%d], gpio request err\n", __func__, __LINE__);\r
+ return -1;\r
+ }\r
+ gpio_direction_output(cs_gpios[i].cs_gpio, GPIO_HIGH);\r
+ }\r
+ }\r
+#endif\r
+ return 0;\r
+}\r
+\r
+static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)\r
+{\r
+#if 1\r
+ int i;\r
+\r
+ if (cs_gpios) {\r
+ for (i=0; i<cs_num; i++) {\r
+ gpio_free(cs_gpios[i].cs_gpio);\r
+ //rk29_mux_api_mode_resume(cs_gpios[i].cs_iomux_name);\r
+ }\r
+ }\r
+#endif\r
+ return 0;\r
+}\r
+\r
+static int spi_io_fix_leakage_bug(void)\r
+{\r
+#if 0\r
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);\r
+#endif\r
+ return 0;\r
+}\r
+\r
+static int spi_io_resume_leakage_bug(void)\r
+{\r
+#if 0\r
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);\r
+#endif\r
+ return 0;\r
+}\r
+\r
+struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {\r
+ .num_chipselect = SPI_CHIPSELECT_NUM,\r
+ .chipselect_gpios = rk29xx_spi0_cs_gpios,\r
+ .io_init = spi_io_init,\r
+ .io_deinit = spi_io_deinit,\r
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,\r
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,\r
+};\r
+\r
+struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {\r
+ .num_chipselect = SPI_CHIPSELECT_NUM,\r
+ .chipselect_gpios = rk29xx_spi1_cs_gpios,\r
+ .io_init = spi_io_init,\r
+ .io_deinit = spi_io_deinit,\r
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,\r
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,\r
+};\r
+\r
+/*****************************************************************************************\r
+ * xpt2046 touch panel\r
+ * author: cmc@rock-chips.com\r
+ *****************************************************************************************/\r
+#define XPT2046_GPIO_INT RK29_PIN0_PA3\r
+#define DEBOUNCE_REPTIME 3\r
+\r
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 0,\r
+ .x_min = 0,\r
+ .x_max = 320,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 0,\r
+ .x_min = 0,\r
+ .x_max = 320,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 1,\r
+ .x_min = 0,\r
+ .x_max = 800,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 1,\r
+ .x_min = 0,\r
+ .x_max = 800,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#endif\r
+\r
+static struct spi_board_info board_spi_devices[] = {\r
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\\r
+ ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)\r
+ {\r
+ .modalias = "xpt2046_ts",\r
+ .chip_select = 0,\r
+ .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */\r
+ .bus_num = 0,\r
+ .irq = XPT2046_GPIO_INT,\r
+ .platform_data = &xpt2046_info,\r
+ },\r
+#endif\r
+};\r
+\r
+\r
+static void __init rk29_gic_init_irq(void)\r
+{\r
+ gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);\r
+ gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);\r
+}\r
+\r
+static void __init machine_rk29_init_irq(void)\r
+{\r
+ rk29_gic_init_irq();\r
+ rk29_gpio_init(rk29_gpiobankinit, MAX_BANK);\r
+ rk29_gpio_irq_setup();\r
+}\r
+#define POWER_ON_PIN RK29_PIN4_PA4\r
+static void __init machine_rk29_board_init(void)\r
+{\r
+ rk29_board_iomux_init();\r
+ gpio_request(POWER_ON_PIN,"poweronpin"); \r
+ gpio_set_value(POWER_ON_PIN, 1);\r
+ gpio_direction_output(POWER_ON_PIN, 1);\r
+
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+ rk29sdk_wifi_bt_gpio_control_init();
+#endif
+\r
+ platform_add_devices(devices, ARRAY_SIZE(devices));\r
+#ifdef CONFIG_I2C0_RK29\r
+ i2c_register_board_info(default_i2c0_data.bus_num, board_i2c0_devices,\r
+ ARRAY_SIZE(board_i2c0_devices));\r
+#endif\r
+#ifdef CONFIG_I2C1_RK29\r
+ i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,\r
+ ARRAY_SIZE(board_i2c1_devices));\r
+#endif\r
+#ifdef CONFIG_I2C2_RK29\r
+ i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,\r
+ ARRAY_SIZE(board_i2c2_devices));\r
+#endif\r
+#ifdef CONFIG_I2C3_RK29\r
+ i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,\r
+ ARRAY_SIZE(board_i2c3_devices));\r
+#endif\r
+\r
+ spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));\r
+}\r
+\r
+static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,\r
+ char **cmdline, struct meminfo *mi)\r
+{\r
+ mi->nr_banks = 1;\r
+ mi->bank[0].start = RK29_SDRAM_PHYS;\r
+ mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);\r
+ mi->bank[0].size = LINUX_SIZE;\r
+}\r
+\r
+static void __init machine_rk29_mapio(void)\r
+{\r
+ rk29_map_common_io();\r
+ rk29_clock_init();\r
+ rk29_iomux_init();\r
+}\r
+\r
+MACHINE_START(RK29, "RK29board")\r
+ /* UART for LL DEBUG */\r
+ .phys_io = RK29_UART1_PHYS,\r
+ .io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,\r
+ .boot_params = RK29_SDRAM_PHYS + 0x88000,\r
+ .fixup = machine_rk29_fixup,\r
+ .map_io = machine_rk29_mapio,\r
+ .init_irq = machine_rk29_init_irq,\r
+ .init_machine = machine_rk29_board_init,\r
+ .timer = &rk29_timer,\r
+MACHINE_END\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff