rk29: reset with softreset and set vcore to 1.2v for fix sdk board dead

diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c
index 9b022708cf9914e4fab002f6f49607170fc131ca..b776f716ec9f1257c099f2c3bcffd3e3626072e1 100755 (executable)
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
@@ -1722,11 +1722,11 @@ void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 {
        unsigned long flags;
 
-       local_irq_save(flags);
        mdelay(10);
+       local_irq_save(flags);
        do_pmu_set_power_domain(pd, on);
-       mdelay(10);
        local_irq_restore(flags);
+       mdelay(10);
 }
 
 static int pd_vcodec_mode(struct clk *clk, int on)

diff --git a/arch/arm/mach-rk29/cpufreq.c b/arch/arm/mach-rk29/cpufreq.c
index 9c62d1c8d26b2e1164338931c163dc3d541aba99..c13a4b3b5ab1db6df835f0c5e679dda1e07f42d5 100755 (executable)
--- a/arch/arm/mach-rk29/cpufreq.c
+++ b/arch/arm/mach-rk29/cpufreq.c
@@ -37,9 +37,9 @@ static int no_cpufreq_access;
 static struct cpufreq_frequency_table freq_table[] = {
 //     { .index =  950000, .frequency =  204000 },
 //     { .index = 1050000, .frequency =  300000 },
-       { .index = 1150000, .frequency =  408000 },
+       { .index = 1200000, .frequency =  408000 },
 //     { .index = 1125000, .frequency =  600000 },
-       { .index = 1150000, .frequency =  816000 },
+       { .index = 1200000, .frequency =  816000 },
 //     { .index = 1250000, .frequency = 1008000 },
 //     { .index = 1300000, .frequency = 1200000 },
        { .frequency = CPUFREQ_TABLE_END },

diff --git a/arch/arm/mach-rk29/reset.c b/arch/arm/mach-rk29/reset.c
index 03097d541f16726428cb1f3ee824a47a5d0b3871..222c7959fb4ffb4810d47131c997b66e96784df8 100755 (executable)
--- a/arch/arm/mach-rk29/reset.c
+++ b/arch/arm/mach-rk29/reset.c
@@ -15,46 +15,15 @@
 #include <mach/cru.h>\r
 #include <mach/memory.h>\r
 #include <mach/sram.h>\r
-#include <linux/clk.h>\r
+#include <mach/pmu.h>\r
 \r
 #include <asm/delay.h>\r
 #include <asm/tlbflush.h>\r
 #include <asm/cacheflush.h>\r
 \r
-static inline void delay_500ns(void)\r
-{\r
-       int delay = 13;\r
-       barrier();\r
-       while (delay--)\r
-               barrier();\r
-}\r
-\r
-\r
-#if 0\r
-volatile int testflag;\r
-static void  __rk29_reset_to_maskrom(void)\r
-{\r
-       u32 reg;\r
-    asm("mrc    p15, 0, %0, c1, c0, 0\n\t"\r
-        "bic    %0, %0, #(1 << 13)  @set vector to 0x00000000\n\t"\r
-        "bic    %0, %0, #(1 << 0)   @disable mmu\n\t"\r
-        "bic    %0, %0, #(1 << 12)  @disable I CACHE\n\t"\r
-        "bic    %0, %0, #(1 << 2)   @disable D DACHE\n\t"\r
-        "bic    %0, %0, #(1 << 11)      @disable \n\t"\r
-        "bic    %0, %0, #(1 << 28)      @disable \n\t"\r
-        "mcr    p15, 0, %0, c1, c0, 0\n\t"\r
-    //      "mcr    p15, 0, %0, c8, c7, 0   @ invalidate whole TLB\n\t"\r
-    //      "mcr    p15, 0, %0, c7, c5, 6   @ invalidate BTC\n\t"\r
-        : "=r" (reg));\r
-\r
-    asm("b 1f\n\t"\r
-        ".align 5\n\t"\r
-        "1:\n\t"\r
-        "mcr    p15, 0, %0, c7, c10, 5\n\t"\r
-        "mcr    p15, 0, %0, c7, c10, 4\n\t"\r
-        "mov    pc, #0" : : "r" (reg));\r
-} \r
-#endif\r
+#define LOOPS_PER_USEC 13\r
+#define LOOPS_PER_MSEC 12000\r
+#define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0)\r
 \r
 static void  pwm2gpiodefault(void)\r
 {\r
@@ -87,8 +56,66 @@ void rb( void )
     cb( uart_base );\r
 }\r
 \r
+static void __sramfunc __noreturn rk29_rb_with_softreset(void)\r
+{\r
+       u32 reg;\r
+\r
+       asm volatile (\r
+           "mrc        p15, 0, %0, c1, c0, 0\n\t"\r
+           "bic        %0, %0, #(1 << 0)       @disable MMU\n\t"\r
+           "bic        %0, %0, #(1 << 13)      @set vector to 0x00000000\n\t"\r
+           "bic        %0, %0, #(1 << 12)      @disable I CACHE\n\t"\r
+           "bic        %0, %0, #(1 << 2)       @disable D DACHE\n\t"\r
+           "bic        %0, %0, #(1 << 11)      @disable Branch prediction\n\t"\r
+            "bic       %0, %0, #(1 << 28)      @disable TEX Remap\n\t"\r
+           "mcr        p15, 0, %0, c1, c0, 0\n\t"\r
+           "mov        %0, #0\n\t"\r
+           "mcr        p15, 0, %0, c8, c7, 0   @invalidate whole TLB\n\t"\r
+           "mcr        p15, 0, %0, c7, c5, 6   @invalidate BTC\n\t"\r
+           "dsb\n\t"\r
+           "isb\n\t"\r
+           "b          1f\n\t"\r
+           ".align 5\n\t"\r
+           "1:\n\t"\r
+           : "=r" (reg));\r
+\r
+       writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
+       dsb();\r
+       LOOP(10 * LOOPS_PER_USEC);\r
+\r
+       writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
+       writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
+       writel(0xd9fdfdc0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
+       dsb();\r
+\r
+       LOOP(100 * LOOPS_PER_USEC);\r
+\r
+       writel(0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
+       writel(0, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
+       writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
+       dsb();\r
+       LOOP(10 * LOOPS_PER_USEC);\r
+       writel(0, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
+       dsb();\r
+       LOOP(10 * LOOPS_PER_USEC);\r
+\r
+       asm volatile (\r
+           "b 1f\n\t"\r
+           ".align 5\n\t"\r
+           "1:\n\t"\r
+           "dsb\n\t"\r
+           "isb\n\t"\r
+           "mov        pc, #0");\r
+\r
+       while (1);\r
+}\r
+\r
 void  rk29_arch_reset(int mode, const char *cmd)\r
 {\r
+       void (*rb2)(void);\r
+\r
+       rb2 = (void(*)(void))((u32)rk29_rb_with_softreset - SRAM_CODE_OFFSET + 0x10130000);\r
+\r
        local_irq_disable();\r
        local_fiq_disable();\r
 \r
@@ -101,7 +128,7 @@ void  rk29_arch_reset(int mode, const char *cmd)
 #endif\r
 \r
        cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);\r
-       delay_500ns();\r
+       LOOP(LOOPS_PER_USEC);\r
 \r
        /* from panic? */\r
        if (system_state != SYSTEM_RESTART)\r
@@ -110,21 +137,45 @@ void  rk29_arch_reset(int mode, const char *cmd)
        pwm2gpiodefault();\r
 \r
        cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);\r
-       delay_500ns();\r
+       LOOP(LOOPS_PER_USEC);\r
 \r
        cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);\r
-       delay_500ns();\r
-       \r
+       LOOP(LOOPS_PER_USEC);\r
+\r
        cru_writel(0, CRU_CLKGATE0_CON);\r
        cru_writel(0, CRU_CLKGATE1_CON);\r
        cru_writel(0, CRU_CLKGATE2_CON);\r
        cru_writel(0, CRU_CLKGATE3_CON);\r
-       delay_500ns();\r
+       LOOP(LOOPS_PER_USEC);\r
 \r
        cru_writel(0, CRU_SOFTRST0_CON);\r
        cru_writel(0, CRU_SOFTRST1_CON);\r
        cru_writel(0, CRU_SOFTRST2_CON);\r
-       \r
+       LOOP(LOOPS_PER_USEC);\r
+\r
+       cru_writel(1 << 16 | 1 << 13 | 1 << 11 | 1 << 1, CRU_CLKGATE3_CON);\r
+       LOOP(LOOPS_PER_USEC);\r
+\r
+       writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_VCODEC), RK29_PMU_BASE + PMU_PD_CON);\r
+       dsb();\r
+       while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_VCODEC))\r
+               ;\r
+       LOOP(10 * LOOPS_PER_MSEC);\r
+\r
+       writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_DISPLAY), RK29_PMU_BASE + PMU_PD_CON);\r
+       dsb();\r
+       while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_DISPLAY))\r
+               ;\r
+       LOOP(10 * LOOPS_PER_MSEC);\r
+\r
+       writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_GPU), RK29_PMU_BASE + PMU_PD_CON);\r
+       dsb();\r
+       while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_GPU))\r
+               ;\r
+       LOOP(10 * LOOPS_PER_MSEC);\r
+\r
+       cru_writel(0, CRU_CLKGATE3_CON);\r
+       LOOP(LOOPS_PER_USEC);\r
 \r
        //SPI0 clock source = periph_pll_clk, SPI0 divider=8\r
        cru_writel((cru_readl(CRU_CLKSEL6_CON) & ~0x1FF) | (7 << 2), CRU_CLKSEL6_CON);\r
@@ -135,17 +186,28 @@ void  rk29_arch_reset(int mode, const char *cmd)
        //UART1 clock divider=0, UART1 clk =24MHz , UART0 and UART1 clock source=periph_pll_clk\r
        cru_writel((cru_readl(CRU_CLKSEL8_CON) & ~(7 | (0x3f << 14) | (3 << 20))) | (2 << 20), CRU_CLKSEL8_CON);\r
 \r
+       // remap bit control = 0, normal mode\r
        writel(readl(RK29_GRF_PHYS + 0xc0) & ~(1 << 21), RK29_GRF_PHYS + 0xc0);\r
+       // emmc_and_boot_en control=0, normal mode\r
        writel(readl(RK29_GRF_PHYS + 0xbc) & ~(1 << 9), RK29_GRF_PHYS + 0xbc);\r
+       dsb();\r
 \r
        writel(0, RK29_CPU_AXI_BUS0_PHYS);\r
        writel(0, RK29_AXI1_PHYS);\r
-\r
-       //__cpuc_flush_kern_all();\r
-       //__cpuc_flush_user_all();\r
+       dsb();\r
+\r
+       // SDMMC_CLKSRC=0, clk_source=clock divider 0\r
+       writel(0, RK29_EMMC_PHYS + 0x0c);\r
+       // SDMMC_CTYPE=0, card_width=1 bit mode\r
+       writel(0, RK29_EMMC_PHYS + 0x18);\r
+       // SDMMC_BLKSIZ=0x200, Block size=512\r
+       writel(0x200, RK29_EMMC_PHYS + 0x1c);\r
+       dsb();\r
+\r
+       __cpuc_flush_kern_all();\r
+       __cpuc_flush_user_all();\r
        \r
-    rb();\r
-\r
+       rb2();\r
 }\r
 \r
 \r