Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218062 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h
index af692de7430b57564ccd5e5c48051ddb7f06934f..42d7dc573284d5bc868c2d4ce839df9393c01e54 100644 (file)
--- a/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/lib/Target/AArch64/AArch64TargetMachine.h
@@ -31,7 +31,6 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL, bool IsLittleEndian);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const AArch64Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index dfbf45d12fd7296faaeaab713d8265c9f2dd2923..3a7887f5edf4be533d9841e8ce45115c282d0f85 100644 (file)
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -32,7 +32,6 @@ public:
                        CodeGenOpt::Level OL,
                        bool isLittle);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register ARM analysis passes with a pass manager.

diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h
index d2bba73c34e907af8d98928f8c66f6d944907957..d917d5b89a1edf4007f7d8fd28adb8a260a5e068 100644 (file)
--- a/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -31,7 +31,6 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const HexagonSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h
index 597629d3e81a5c143d491ce965af4dffc3801837..5c73c831f5e0b0efae1fc1730d3e37b8ecb2854c 100644 (file)
--- a/lib/Target/MSP430/MSP430TargetMachine.h
+++ b/lib/Target/MSP430/MSP430TargetMachine.h
@@ -32,7 +32,6 @@ public:
                       Reloc::Model RM, CodeModel::Model CM,
                       CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const MSP430Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index 43b6256234682914188eb28a9ac34de9007e840f..58400cd1b48e7ee803251194d475d1d5b18a278b 100644 (file)
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -39,7 +39,6 @@ public:
 
   void addAnalysisPasses(PassManagerBase &PM) override;
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const MipsSubtarget *getSubtargetImpl() const override {
     if (Subtarget)
       return Subtarget;

diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h
index 7cc03cb7de87c2793ce55460ba710090dc32f59c..3dca4da724a315352c608db061813dd83fdc00a5 100644 (file)
--- a/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ b/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -35,7 +35,6 @@ public:
                      const TargetOptions &Options, Reloc::Model RM,
                      CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   ManagedStringPool *getManagedStrPool() const {

diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index c503ec2fdc7d9a8fdc7a350b8c276bc20afdb7dd..ea7f27ae18a72a1dc229b53c3f15494b43da90e3 100644 (file)
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -32,7 +32,6 @@ public:
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration

diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h
index 14411e97bb999415a61ad654533e0ea45f11d38e..ff581b5c9aad73426af64331ade7aa56a23970e9 100644 (file)
--- a/lib/Target/R600/AMDGPUTargetMachine.h
+++ b/lib/Target/R600/AMDGPUTargetMachine.h
@@ -33,8 +33,6 @@ public:
                       StringRef CPU, TargetOptions Options, Reloc::Model RM,
                       CodeModel::Model CM, CodeGenOpt::Level OL);
   ~AMDGPUTargetMachine();
-
-  using LLVMTargetMachine::getSubtargetImpl;
   const AMDGPUSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index 4b071ba937866f68c18f2709b05774bea42dfa0a..142929ca60eb3c5218cc52dad86bed85950b482c 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -28,7 +28,6 @@ public:
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL, bool is64bit);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration

diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h
index 45ff61f6b78c9af5e5e3c98ee86953fbb88e0122..c5f982395a1397be03a6da8d22722252069bdf0b 100644 (file)
--- a/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -32,7 +32,6 @@ public:
                        CodeGenOpt::Level OL);
 
   // Override TargetMachine.
-  using LLVMTargetMachine::getSubtargetImpl;
   const SystemZSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index b7042e1f0a726d36962f7538d7f47228c3a42b57..8783bab5d950d749045ed37fd60489af07f6f74a 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -31,8 +31,6 @@ public:
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
-
-  using LLVMTargetMachine::getSubtargetImpl;
   const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register X86 analysis passes with a pass manager.

diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h
index e6654f3b0627c73deb6a3991956be4e2223287cc..32360996bbaaba0bf7d491df281a7ea6bc5e96ab 100644 (file)
--- a/lib/Target/XCore/XCoreTargetMachine.h
+++ b/lib/Target/XCore/XCoreTargetMachine.h
@@ -27,7 +27,6 @@ public:
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration