Fix my brain cramp by inverting the assertion condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76131 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 2213c65f343b613dd93f02702fc79627d239da88..abaa8bd212e94635cb84b48c6eb6d83b0112f432 100644 (file)
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -491,12 +491,10 @@ static void ReMaterialize(MachineBasicBlock &MBB,
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
   MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
-#if 0
 #ifndef NDEBUG
   const TargetInstrDesc &TID = ReMatDefMI->getDesc();
-  assert(TID.getNumDefs() != 1 &&
+  assert(TID.getNumDefs() == 1 &&
          "Don't know how to remat instructions that define > 1 values!");
-#endif
 #endif
   TII->reMaterialize(MBB, MII, DestReg,
                      ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);