Moving options declarations around.

More short term hackery until we have a way to configure passes that work on LiveIntervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148289 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index cb22b1826d9bad7300a160931d5ff18c31b01662..3f42bbe16a03dbdc191cb517ca3e22cb84c5377b 100644 (file)
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -34,10 +34,6 @@ namespace llvm {
   /// wth earlier copy coalescing.
   extern bool StrongPHIElim;
 
-  /// EnableMachineSched - temporary flag to enable the machine scheduling pass
-  /// until we complete the register allocation pass configuration cleanup.
-  extern bool EnableMachineSched;
-
   class TargetOptions {
   public:
     TargetOptions()

diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index cb92513d8ec1567fd8ff1110fe3f1c407b984725..dbddf722d169d9a4126289144892f0af95637edd 100644 (file)
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -149,8 +149,6 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
   if (StrongPHIElim)
     AU.addRequiredID(StrongPHIEliminationID);
   AU.addRequiredTransitiveID(RegisterCoalescerPassID);
-  if (EnableMachineSched)
-    AU.addRequiredID(MachineSchedulerPassID);
   AU.addRequired<CalculateSpillWeights>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();

diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index bced80ca5405501e9bff6691a5c669fe7385fc9e..16832ceaf3df037133100bb9b658fa2e17eea945 100644 (file)
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -51,6 +51,13 @@ STATISTIC(NumGlobalSplits, "Number of split global live ranges");
 STATISTIC(NumLocalSplits,  "Number of split local live ranges");
 STATISTIC(NumEvicted,      "Number of interferences evicted");
 
+/// EnableMachineSched - temporary flag to enable the machine scheduling pass
+/// until we complete the register allocation pass configuration cleanup.
+static cl::opt<bool>
+EnableMachineSched("enable-misched",
+                   cl::desc("Enable the machine instruction scheduling pass."),
+                   cl::init(false), cl::Hidden);
+
 static cl::opt<SplitEditor::ComplementSpillMode>
 SplitSpillMode("split-spill-mode", cl::Hidden,
   cl::desc("Spill mode for splitting live ranges"),

diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index 90042dc1d5282aed18de1f591041410cde73b992..19819b886c11e38e794e4d1bfd3a430172dc1e34 100644 (file)
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -37,14 +37,6 @@ FunctionSections("ffunction-sections",
   cl::desc("Emit functions into separate sections"),
   cl::init(false));
 
-/// EnableMachineSched - temporary flag to enable the machine scheduling pass
-/// until we complete the register allocation pass configuration cleanup.
-static cl::opt<bool, true>
-MachineSchedOpt("enable-misched",
-                cl::desc("Enable the machine instruction scheduling pass."),
-                cl::location(EnableMachineSched),
-                cl::init(false), cl::Hidden);
-
 //---------------------------------------------------------------------------
 // TargetMachine Class
 //