Add a utility routine to check for unpredicated terminator instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index f03fbb532143fd4608a8a83c595707794bb14c85..2571db4e01ae5b858e0a26b33d0e08682dcad7d2 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -399,19 +399,23 @@ public:
     abort();
   }
 
-  /// isPredicable - Returns true if the instruction is already predicated.
+  /// isPredicated - Returns true if the instruction is already predicated.
   ///
   virtual bool isPredicated(const MachineInstr *MI) const {
     return false;
   }
 
+  /// isUnpredicatedTerminator - Returns true if the instruction is a
+  /// terminator instruction that has not been predicated.
+  bool isUnpredicatedTerminator(const MachineInstr *MI) const;
+
   /// PredicateInstruction - Convert the instruction into a predicated
   /// instruction. It returns true if the operation was successful.
   virtual
   bool PredicateInstruction(MachineInstr *MI,
                             const std::vector<MachineOperand> &Pred) const;
 
-  /// SubsumesPredicate - Returns true if the first specified predicated
+  /// SubsumesPredicate - Returns true if the first specified predicate
   /// subsumes the second, e.g. GE subsumes GT.
   virtual
   bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 0d0b813914637c9e560354186cc3876dd455c249..e9c57b25e48ddded72b20c4799697d95d9a1e0e0 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -304,7 +304,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  std::vector<MachineOperand> &Cond) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
     return false;
   
   // Get the last instruction in the block.
@@ -313,7 +313,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
   if (I == MBB.begin() ||
-      isPredicated(--I) || !isTerminatorInstr(I->getOpcode())) {
+      isPredicated(--I) || !isUnpredicatedTerminator(I)) {
     if (LastOpc == ARM::B || LastOpc == ARM::tB) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -332,7 +332,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
   
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() &&
-      !isPredicated(--I) && isTerminatorInstr(I->getOpcode()))
+      !isPredicated(--I) && isUnpredicatedTerminator(I))
     return true;
   
   // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 299a6071488ec3c148c137ca08f24ec70b519587..15f5f841bc3fa8164dc0e43facdc0b977290d9eb 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -158,14 +158,14 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
                                  std::vector<MachineOperand> &Cond) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
     return false;
 
   // Get the last instruction in the block.
   MachineInstr *LastInst = I;
   
   // If there is only one terminator instruction, process it.
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (LastInst->getOpcode() == Alpha::BR) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -186,7 +186,7 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
 
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() &&
-      isTerminatorInstr((--I)->getOpcode()))
+      isUnpredicatedTerminator(--I))
     return true;
   
   // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7659a570800320de30369271a35cbc2eae5e0f44..1ec9e6013876564fb7722077918d303696b4613b 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -180,14 +180,14 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  std::vector<MachineOperand> &Cond) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
     return false;
 
   // Get the last instruction in the block.
   MachineInstr *LastInst = I;
   
   // If there is only one terminator instruction, process it.
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (LastInst->getOpcode() == PPC::B) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -207,7 +207,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() &&
-      isTerminatorInstr((--I)->getOpcode()))
+      isUnpredicatedTerminator(--I))
     return true;
   
   // If the block ends with PPC::B and PPC:BCC, handle it.

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 56ec835a119784b3a1c77021133bdb4e0ed666e0..6f6083fb2825612f6f8485d6d4bf99ce2cd8046e 100644 (file)
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -84,3 +84,10 @@ bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
   }
   return MadeChange;
 }
+
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_TERMINATOR_FLAG)
+    return !isPredicated(MI);
+  return false;
+}

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 291c3dce08520cc7c510d7076f5fc80140bc180e..a3b3223611e016271b2203bb5d5981762bb21eef 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -382,14 +382,14 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
                                    
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
     return false;
 
   // Get the last instruction in the block.
   MachineInstr *LastInst = I;
   
   // If there is only one terminator instruction, process it.
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (!isBranch(LastInst->getOpcode()))
       return true;