Thumb2 assembly parsing and encoding for MSR/MRS.

Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 15ca72449126beacb952cbb9f1a18cc443ecb020..6ef443e95242c5bf4617bee0160436acfab4cfbc 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3507,49 +3507,39 @@ defm t2STC  : T2LdStCop<0b1111, 0, "stc">;
 //===----------------------------------------------------------------------===//
 // Move between special register and ARM core register -- for disassembly only
 //
-
-class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
-          dag oops, dag iops, InstrItinClass itin,
-          string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
-  let Inst{31-20} = op31_20{11-0};
-  let Inst{15-14} = op15_14{1-0};
-  let Inst{13}    = 0b0;
-  let Inst{12} = op12{0};
-  let Inst{7-0}   = 0;
+// Move to ARM core register from Special Register
+def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
+  bits<4> Rd;
+  let Inst{31-12} = 0b11110011111011111000;
+  let Inst{11-8} = Rd;
+  let Inst{7-0} = 0b0000;
 }
 
-class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
-          dag oops, dag iops, InstrItinClass itin,
-          string opc, string asm, list<dag> pattern>
-  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
+def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
+
+def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
   bits<4> Rd;
+  let Inst{31-12} = 0b11110011111111111000;
   let Inst{11-8} = Rd;
-  let Inst{19-16} = 0b1111;
+  let Inst{7-0} = 0b0000;
 }
 
-def t2MRS : T2MRS<0b111100111110, 0b10, 0,
-                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
-                [/* For disassembly only; pattern left blank */]>;
-def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
-                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
-                   [/* For disassembly only; pattern left blank */]>;
-
 // Move from ARM core register to Special Register
 //
 // No need to have both system and application versions, the encodings are the
 // same and the assembly parser has no way to distinguish between them. The mask
 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
 // the mask with the fields to be accessed in the special register.
-def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
-                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
-                         NoItinerary, "msr", "\t$mask, $Rn",
-                         [/* For disassembly only; pattern left blank */]> {
+def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
+                NoItinerary, "msr", "\t$mask, $Rn", []> {
   bits<5> mask;
   bits<4> Rn;
-  let Inst{19-16} = Rn;
+  let Inst{31-21} = 0b11110011100;
   let Inst{20}    = mask{4}; // R Bit
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = 0b1000;
   let Inst{11-8}  = mask{3-0};
+  let Inst{7-0}   = 0;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index dc310a183dc95df0c03d8e1b95adf9f5ce284463..9453c3d7dd7bbaf794f11af00e13508871b4b779 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2077,7 +2077,7 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
       if (!Flags.empty())
         return MatchOperand_NoMatch;
       else
-        FlagsVal = 0; // No flag
+        FlagsVal = 8; // No flag
     }
   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
     if (Flags == "all") // cpsr_all is an alias for cpsr_fc

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 706c61c0473783d8d6a09fd4612ee42331c1a727..8691e15e162b21c433fe479aa4c6c9eba068dd72 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -838,7 +838,7 @@ Lforward:
         msr  SPSR_fsxc, #5
         msr  cpsr_fsxc, #5
 
-@ CHECK: msr   CPSR_fc, #5             @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr   APSR_nzcvq, #5          @ encoding: [0x05,0xf0,0x28,0xe3]
 @ CHECK: msr   APSR_g, #5              @ encoding: [0x05,0xf0,0x24,0xe3]
 @ CHECK: msr   APSR_nzcvq, #5          @ encoding: [0x05,0xf0,0x28,0xe3]
 @ CHECK: msr   APSR_nzcvq, #5          @ encoding: [0x05,0xf0,0x28,0xe3]
@@ -868,7 +868,7 @@ Lforward:
         msr  SPSR_fsxc, r0
         msr  cpsr_fsxc, r0
 
-@ CHECK: msr  CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr  APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
 @ CHECK: msr  APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
 @ CHECK: msr  APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
 @ CHECK: msr  APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]

diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index b51fb8c41ba4fd26d1ed74ea50faa98b5a60c351..bb399868b8cfa4020f754adf245db687f030548a 100644 (file)
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -1062,6 +1062,52 @@ _func:
 @ CHECK: mrrc2 p7, #1, r5, r4, c1      @ encoding: [0x54,0xfc,0x11,0x57]
 
 
+@------------------------------------------------------------------------------
+@ MRS
+@------------------------------------------------------------------------------
+        mrs  r8, apsr
+        mrs  r8, cpsr
+        mrs  r8, spsr
+
+@ CHECK: mrs   r8, apsr                @ encoding: [0xef,0xf3,0x00,0x88]
+@ CHECK: mrs   r8, apsr                @ encoding: [0xef,0xf3,0x00,0x88]
+@ CHECK: mrs   r8, spsr                @ encoding: [0xff,0xf3,0x00,0x88]
+
+
+@------------------------------------------------------------------------------
+@ MSR
+@------------------------------------------------------------------------------
+        msr  apsr, r1
+        msr  apsr_g, r2
+        msr  apsr_nzcvq, r3
+        msr  APSR_nzcvq, r4
+        msr  apsr_nzcvqg, r5
+        msr  cpsr_fc, r6
+        msr  cpsr_c, r7
+        msr  cpsr_x, r8
+        msr  cpsr_fc, r9
+        msr  cpsr_all, r11
+        msr  cpsr_fsx, r12
+        msr  spsr_fc, r0
+        msr  SPSR_fsxc, r5
+        msr  cpsr_fsxc, r8
+
+@ CHECK: msr   APSR_nzcvq, r1          @ encoding: [0x81,0xf3,0x00,0x88]
+@ CHECK: msr   APSR_g, r2              @ encoding: [0x82,0xf3,0x00,0x84]
+@ CHECK: msr   APSR_nzcvq, r3          @ encoding: [0x83,0xf3,0x00,0x88]
+@ CHECK: msr   APSR_nzcvq, r4          @ encoding: [0x84,0xf3,0x00,0x88]
+@ CHECK: msr   APSR_nzcvqg, r5         @ encoding: [0x85,0xf3,0x00,0x8c]
+@ CHECK: msr   CPSR_fc, r6             @ encoding: [0x86,0xf3,0x00,0x89]
+@ CHECK: msr   CPSR_c, r7              @ encoding: [0x87,0xf3,0x00,0x81]
+@ CHECK: msr   CPSR_x, r8              @ encoding: [0x88,0xf3,0x00,0x82]
+@ CHECK: msr   CPSR_fc, r9             @ encoding: [0x89,0xf3,0x00,0x89]
+@ CHECK: msr   CPSR_fc, r11            @ encoding: [0x8b,0xf3,0x00,0x89]
+@ CHECK: msr   CPSR_fsx, r12           @ encoding: [0x8c,0xf3,0x00,0x8e]
+@ CHECK: msr   SPSR_fc, r0             @ encoding: [0x90,0xf3,0x00,0x89]
+@ CHECK: msr   SPSR_fsxc, r5           @ encoding: [0x95,0xf3,0x00,0x8f]
+@ CHECK: msr   CPSR_fsxc, r8           @ encoding: [0x88,0xf3,0x00,0x8f]
+
+
 @------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------