ARM: sunxi: dt: Convert to the new clock compatibles
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 6 Feb 2014 08:55:58 +0000 (09:55 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Tue, 18 Feb 2014 15:53:37 +0000 (16:53 +0100)
Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i-a10s.dtsi
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun7i-a20.dtsi

index b268f68cf8faeefef26c1ac087623733344992ed..5b18f7d94853320b317a5efe1db8a4ff047e167e 100644 (file)
@@ -60,7 +60,7 @@
 
                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
                        clock-output-names = "osc24M";
@@ -75,7 +75,7 @@
 
                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll1";
@@ -83,7 +83,7 @@
 
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll4";
@@ -91,7 +91,7 @@
 
                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
@@ -99,7 +99,7 @@
 
                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
                        clock-output-names = "cpu";
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
                        clock-output-names = "axi";
 
                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "ahb";
 
                ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-ahb-gates-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb>;
                        clock-output-names = "ahb_usb0", "ahb_ehci0",
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
                        clock-output-names = "apb0";
 
                apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-apb0-gates-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb0>;
                        clock-output-names = "apb0_codec", "apb0_spdif",
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1_mux";
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
 
                apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-apb1-gates-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb1>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
 
                mmc3_clk: clk@01c20094 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc3";
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
 
                pata_clk: clk@01c200ac {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "pata";
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
 
                ir1_clk: clk@01c200b4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir1";
 
                spi3_clk: clk@01c200d4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200d4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi3";
index 0e0da137279ff9c094c2a50380065f3e34c2b8c4..9cbd88421dbcc95066e740c228edb3d89f7e543a 100644 (file)
@@ -53,7 +53,7 @@
 
                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
                        clock-output-names = "osc24M";
@@ -68,7 +68,7 @@
 
                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll1";
@@ -76,7 +76,7 @@
 
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll4";
@@ -84,7 +84,7 @@
 
                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
@@ -92,7 +92,7 @@
 
                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
                        clock-output-names = "cpu";
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
                        clock-output-names = "axi";
 
                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "ahb";
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
                        clock-output-names = "apb0";
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1_mux";
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
 
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
index b1468b3c7c574d7ad36126777eae0a99c34f05f6..6caf65dbf187ec5b00340a2f937ff1b4b4b478b6 100644 (file)
@@ -54,7 +54,7 @@
 
                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
                        clock-output-names = "osc24M";
@@ -69,7 +69,7 @@
 
                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll1";
@@ -77,7 +77,7 @@
 
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll4";
@@ -85,7 +85,7 @@
 
                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
@@ -93,7 +93,7 @@
 
                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
                        clock-output-names = "cpu";
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
                        clock-output-names = "axi";
 
                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-axi-gates-clk";
+                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "ahb";
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
                        clock-output-names = "apb0";
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1_mux";
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
 
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
index d3f19951d501ad9145b0939de7657e61449d3369..af6f87c4e1c7667d98c5cffef70dfef8c793e0c5 100644 (file)
@@ -95,7 +95,7 @@
 
                cpu: cpu@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20050 0x4>;
 
                        /*
 
                axi: axi@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20050 0x4>;
                        clocks = <&cpu>;
                        clock-output-names = "axi";
 
                ahb1: ahb1@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb1_mux>;
                        clock-output-names = "ahb1";
 
                apb1: apb1@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb1>;
                        clock-output-names = "apb1";
 
                apb2_mux: apb2_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
                        clock-output-names = "apb2_mux";
index 25ba9fa99c5d6e0de9f959b0bf534bcc7893799a..bc528de39f8ed14da219890335c17c539e0dd5bb 100644 (file)
@@ -64,7 +64,7 @@
 
                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-osc-clk";
+                       compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
                        clock-output-names = "osc24M";
@@ -79,7 +79,7 @@
 
                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll1";
@@ -87,7 +87,7 @@
 
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-pll1-clk";
+                       compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll4";
@@ -95,7 +95,7 @@
 
                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll5-clk";
+                       compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
 
                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-pll6-clk";
+                       compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
 
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
+                       compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
                        clock-output-names = "cpu";
 
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-axi-clk";
+                       compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
                        clock-output-names = "axi";
 
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-ahb-clk";
+                       compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "ahb";
 
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb0-clk";
+                       compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
                        clock-output-names = "apb0";
 
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                        clock-output-names = "apb1_mux";
 
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
 
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
 
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
 
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
 
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
 
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
 
                mmc3_clk: clk@01c20094 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc3";
 
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
 
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
 
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
 
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
 
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
 
                pata_clk: clk@01c200ac {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "pata";
 
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
 
                ir1_clk: clk@01c200b4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir1";
 
                spi3_clk: clk@01c200d4 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200d4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi3";
 
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
                        clock-output-names = "mbus";