ARM: dts: Add PMU dt data to support PMU for exynos4x12
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 17 Mar 2014 21:25:58 +0000 (06:25 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 17 Mar 2014 21:25:58 +0000 (06:25 +0900)
ARM CPU has its own performance profiling unit(PMU, Perforamnce Monitoring Unit).
This patch add PMU dt data to support PMU which count cache hit and miss events.

PMU interrput list of Exynos4212
- <2 2> : INTG2[2] - PMUIRQ[0] for CPU0
- <3 2> : INTG3[2] - PMUIRQ[1] for CPU1

PMU interrput list of Exynos4412
- <2 2> : INTG2[2], PMUIRQ[0] for CPU0
- <3 2> : INTG3[2], PMUIRQ[1] for CPU1
- <18 2> : INTG18[2], PMUIRQ[2] : CPU2
- <19 2> : INTG19[2], PMUIRQ[3] : CPU3

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/boot/dts/exynos4x12.dtsi

index eec1e304435ecca1edc817bbab27aacd18cb8d66..a1e76ec60e0aae5dbbcc5ea75a12fdeeda54d2a7 100644 (file)
                mshc0 = &mshc_0;
        };
 
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupt-parent = <&combiner>;
+               interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+       };
+
        pd_isp: isp-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;