Add braces for legibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index bcaf6623393cd310fcb920c0aa4a481cefad5830..7bc7b4ae01bd4255814eba1158590a3d293408c8 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -289,7 +289,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
   }
 
   // Match simple R +/- imm12 operands.
-  if (N.getOpcode() == ISD::ADD)
+  if (N.getOpcode() == ISD::ADD) {
     if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
       int RHSC = (int)RHS->getZExtValue();
       if ((RHSC >= 0 && RHSC < 0x1000) ||
@@ -312,6 +312,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
         return true;
       }
     }
+  }
 
   // Otherwise this is R +/- [possibly shifted] R.
   ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;