Remove getAllocatedRegNum(). Use getReg() instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 5e8845eb451a1831b8f2b95b4bd62475870611b0..a1507c8d23d11609b43d3d92a360f6d56f6c7393 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -277,15 +277,12 @@ public:
   }
 
   // used to get the reg number if when one is allocated
-  int getAllocatedRegNum() const {
+  unsigned getReg() const {
     assert(hasAllocatedReg());
     return regNum;
   }
 
   // ********** TODO: get rid of this duplicate code! ***********
-  unsigned getReg() const {
-    return getAllocatedRegNum();
-  }    
   void setReg(unsigned Reg) {
     assert(hasAllocatedReg() && "This operand cannot have a register number!");
     regNum = Reg;

diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index f9f67c74240fffc0ddf4b93812c761b27a0a4cb7..3b268ced41855441cf0fa6b71cff1053946e24e7 100644 (file)
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -149,7 +149,7 @@ public:
 
   // returns the register that is hardwired to zero if any (-1 if none)
   //
-  virtual int getZeroRegNum() const = 0;
+  virtual unsigned getZeroRegNum() const = 0;
 
   // Number of registers used for passing int args (usually 6: %o0 - %o5)
   // and float args (usually 32: %f0 - %f31)

diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 01ca36ff6a18ffc254cfb0485f6a8478fa0a5432..0547159e72246097ec4d3b0425052d40678c5a11 100644 (file)
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -487,11 +487,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
     // if this references a register other than the hardwired
     // "zero" register, record the reference.
     if (mop.hasAllocatedReg()) {
-      int regNum = mop.getAllocatedRegNum();
+      unsigned regNum = mop.getReg();
       
       // If this is not a dummy zero register, record the reference in order
       if (regNum != target.getRegInfo().getZeroRegNum())
-        regToRefVecMap[mop.getAllocatedRegNum()]
+        regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i));
 
       // If this is a volatile register, add the instruction to callDepVec
@@ -528,9 +528,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
   for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
     const MachineOperand& mop = MI.getImplicitOp(i);
     if (mop.hasAllocatedReg()) {
-      int regNum = mop.getAllocatedRegNum();
+      unsigned regNum = mop.getReg();
       if (regNum != target.getRegInfo().getZeroRegNum())
-        regToRefVecMap[mop.getAllocatedRegNum()]
+        regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i + MI.getNumOperands()));
       continue;                     // nothing more to do
     }

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 9bee8955fa766f5d8e9ffeb89b7b2e70c99d94e8..22cdb4f8842886a4611ae5e3a1cb9b0bd64f9f4c 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -115,7 +115,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
                 const MachineOperand& mop = mi->getOperand(i);
                 if (mop.isRegister() &&
                     MRegisterInfo::isVirtualRegister(mop.getReg())) {
-                    unsigned reg = mop.getAllocatedRegNum();
+                    unsigned reg = mop.getReg();
                     Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
                     assert(r2iit != r2iMap_.end());
                     r2iit->second->weight += pow(10.0F, loopDepth);
@@ -313,7 +313,7 @@ void LiveIntervals::computeIntervals()
                 MachineOperand& mop = mi->getOperand(i);
                 // handle register defs - build intervals
                 if (mop.isRegister() && mop.isDef())
-                    handleRegisterDef(mbb, mi, mop.getAllocatedRegNum());
+                    handleRegisterDef(mbb, mi, mop.getReg());
             }
         }
     }

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index b5ffd6215a82bda32e7cd80c3c5cdee979f7faea..ca2c2db4a8480ea467bb105d51b8a12b0d141ca9 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -187,7 +187,7 @@ static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
 static inline void OutputReg(std::ostream &os, unsigned RegNo,
                              const MRegisterInfo *MRI = 0) {
   if (MRI) {
-    if (RegNo < MRegisterInfo::FirstVirtualRegister)
+    if (MRegisterInfo::isPhysicalRegister(RegNo))
       os << "%" << MRI->get(RegNo).Name;
     else
       os << "%reg" << RegNo;
@@ -219,14 +219,14 @@ static void print(const MachineOperand &MO, std::ostream &OS,
         OS << "==";
     }
     if (MO.hasAllocatedReg())
-      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+      OutputReg(OS, MO.getReg(), MRI);
     break;
   case MachineOperand::MO_CCRegister:
     OS << "%ccreg";
     OutputValue(OS, MO.getVRegValue());
     if (MO.hasAllocatedReg()) {
       OS << "==";
-      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+      OutputReg(OS, MO.getReg(), MRI);
     }
     break;
   case MachineOperand::MO_MachineRegister:
@@ -360,7 +360,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
     {
     case MachineOperand::MO_VirtualRegister:
       if (MO.hasAllocatedReg())
-        OutputReg(OS, MO.getAllocatedRegNum());
+        OutputReg(OS, MO.getReg());
 
       if (MO.getVRegValue()) {
        if (MO.hasAllocatedReg()) OS << "==";
@@ -373,7 +373,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
       OutputValue(OS, MO.getVRegValue());
       if (MO.hasAllocatedReg()) {
         OS << "==";
-        OutputReg(OS, MO.getAllocatedRegNum());
+        OutputReg(OS, MO.getReg());
       }
       break;
     case MachineOperand::MO_MachineRegister:

diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 03a1da9f13d6c0ad557c97428c70166ff0815bad..e0025f9e4fa2420003447fd2d062f852d6f9912b 100644 (file)
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -76,7 +76,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
     assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
            "PHI node doesn't write virt reg?");
 
-    unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
+    unsigned DestReg = MI->getOperand(0).getReg();
     
     // Create a new register for the incoming PHI arguments
     const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index b9d6f0846fe11e2f9bc96fd61df1f66236dfbd1f..d26ee8f8c5747f3700c320d1daf6a7a04e76f504 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -443,7 +443,7 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
                 MachineOperand& op = currentInstr_->getOperand(i);
                 if (op.isRegister() && op.isUse() &&
                     MRegisterInfo::isVirtualRegister(op.getReg())) {
-                    unsigned virtReg = op.getAllocatedRegNum();
+                    unsigned virtReg = op.getReg();
                     unsigned physReg = 0;
                     Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
                     if (it != v2pMap_.end()) {

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index afbc7eb0e12b59f3ea31d721ee9b52de4c194461..f9abd68e14a000066a5cf429caeb7b10cdb165d5 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -517,7 +517,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
       if (MI->getOperand(i).isUse() &&
           !MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
           MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
-        unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
+        unsigned VirtSrcReg = MI->getOperand(i).getReg();
         unsigned PhysSrcReg = reloadVirtReg(MBB, MI, VirtSrcReg);
         MI->SetMachineOperandReg(i, PhysSrcReg);  // Assign the input register
       }
@@ -551,7 +551,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
       if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
           MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
-        unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
+        unsigned Reg = MI->getOperand(i).getReg();
         spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         PhysRegsUseOrder.push_back(Reg);
@@ -584,7 +584,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
       if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
           MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
-        unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
+        unsigned DestVirtReg = MI->getOperand(i).getReg();
         unsigned DestPhysReg;
 
         // If DestVirtReg already has a value, use it.

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index a40ec64077bdf523e157a629ac86aac2c08647d1..e313004ff488ce66a50596d31f0f50b20cd5da9b 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
       MachineOperand &op = MI->getOperand(i);
       
       if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
-        unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+        unsigned virtualReg = (unsigned) op.getReg();
         DEBUG(std::cerr << "op: " << op << "\n");
         DEBUG(std::cerr << "\t inst[" << i << "]: ";
               MI->print(std::cerr, *TM));
@@ -187,11 +187,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
               assert(MI->getOperand(1).isRegister()  &&
-                     MI->getOperand(1).getAllocatedRegNum() &&
+                     MI->getOperand(1).getReg() &&
                      MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
-              physReg = MI->getOperand(1).getAllocatedRegNum();
+              physReg = MI->getOperand(1).getReg();
             } else {
               physReg = getFreeReg(virtualReg);
             }
@@ -205,7 +205,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         }
         MI->SetMachineOperandReg(i, physReg);
         DEBUG(std::cerr << "virt: " << virtualReg << 
-              ", phys: " << op.getAllocatedRegNum() << "\n");
+              ", phys: " << op.getReg() << "\n");
       }
     }
     RegClassIdx.clear();

diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 3f99f2a47940aa3b592b93885b6a4eec0a701b60..8dc2ffe365d7060478d24615957e915cc2d9216b 100644 (file)
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -97,14 +97,14 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
             DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
 
             assert(mi->getOperand(1).isRegister() &&
-                   mi->getOperand(1).getAllocatedRegNum() &&
+                   mi->getOperand(1).getReg() &&
                    mi->getOperand(1).isUse() &&
                    "two address instruction invalid");
 
             // if the two operands are the same we just remove the use
             // and mark the def as def&use
-            if (mi->getOperand(0).getAllocatedRegNum() ==
-                mi->getOperand(1).getAllocatedRegNum()) {
+            if (mi->getOperand(0).getReg() ==
+                mi->getOperand(1).getReg()) {
             }
             else {
                 MadeChange = true;
@@ -114,8 +114,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
                 // to:
                 //     a = b
                 //     a = a op c
-                unsigned regA = mi->getOperand(0).getAllocatedRegNum();
-                unsigned regB = mi->getOperand(1).getAllocatedRegNum();
+                unsigned regA = mi->getOperand(0).getReg();
+                unsigned regB = mi->getOperand(1).getReg();
 
                 assert(MRegisterInfo::isVirtualRegister(regA) &&
                        MRegisterInfo::isVirtualRegister(regB) &&
@@ -127,7 +127,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
                 // because we are in SSA form.
                 for (unsigned i = 1; i != mi->getNumOperands(); ++i)
                     assert(!mi->getOperand(i).isRegister() ||
-                           mi->getOperand(i).getAllocatedRegNum() != (int)regA);
+                           mi->getOperand(i).getReg() != regA);
 
                 const TargetRegisterClass* rc =
                     MF.getSSARegMap()->getRegClass(regA);

diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 01ca36ff6a18ffc254cfb0485f6a8478fa0a5432..0547159e72246097ec4d3b0425052d40678c5a11 100644 (file)
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -487,11 +487,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
     // if this references a register other than the hardwired
     // "zero" register, record the reference.
     if (mop.hasAllocatedReg()) {
-      int regNum = mop.getAllocatedRegNum();
+      unsigned regNum = mop.getReg();
       
       // If this is not a dummy zero register, record the reference in order
       if (regNum != target.getRegInfo().getZeroRegNum())
-        regToRefVecMap[mop.getAllocatedRegNum()]
+        regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i));
 
       // If this is a volatile register, add the instruction to callDepVec
@@ -528,9 +528,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
   for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
     const MachineOperand& mop = MI.getImplicitOp(i);
     if (mop.hasAllocatedReg()) {
-      int regNum = mop.getAllocatedRegNum();
+      unsigned regNum = mop.getReg();
       if (regNum != target.getRegInfo().getZeroRegNum())
-        regToRefVecMap[mop.getAllocatedRegNum()]
+        regToRefVecMap[mop.getReg()]
           .push_back(std::make_pair(node, i + MI.getNumOperands()));
       continue;                     // nothing more to do
     }

diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index 131107b991e4879b03b3bcd283fc5e95adcb52b7..a7923862cfa742f5699f42a6085d03e3f7fbfcac 100644 (file)
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -71,7 +71,8 @@ ChooseRegOrImmed(int64_t intValue,
       opType = isSigned? MachineOperand::MO_SignExtendedImmed
                        : MachineOperand::MO_UnextendedImmed;
       getImmedValue = intValue;
-  } else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0) {
+  } else if (intValue == 0 &&
+             target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
     opType = MachineOperand::MO_MachineRegister;
     getMachineRegNum = target.getRegInfo().getZeroRegNum();
   }

diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index f28ca86c708b8df3034c03e9ad5aef3884d0a23c..100f9eb4c6290482546531424e38fe53829844f9 100644 (file)
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -194,9 +194,8 @@ void LiveRangeInfo::constructLiveRanges() {
           // set it directly in the LiveRange
           if (OpI.getMachineOperand().hasAllocatedReg()) {
             unsigned getClassId;
-            LR->setColor(MRI.getClassRegNum(
-                                OpI.getMachineOperand().getAllocatedRegNum(),
-                                getClassId));
+            LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
+                                            getClassId));
           }
        }
 
@@ -212,7 +211,7 @@ void LiveRangeInfo::constructLiveRanges() {
           if (MInst->getImplicitOp(i).hasAllocatedReg()) {
             unsigned getClassId;
             LR->setColor(MRI.getClassRegNum(
-                                MInst->getImplicitOp(i).getAllocatedRegNum(),
+                                MInst->getImplicitOp(i).getReg(),
                                 getClassId));
           }
        }

diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 4a7d503f5b21b7e58a18b4a52ee1393164ec6e8d..cc019b478a78a1b125789e1d6acaf88db030e494 100644 (file)
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -1019,12 +1019,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
   // explicit and implicit operands are set.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
     if (MI->getOperand(i).hasAllocatedReg())
-      markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
+      markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
 
   for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
     if (MI->getImplicitOp(i).hasAllocatedReg())
-      markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
-                       RegType,MRI);
+      markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
 
   // Add all of the scratch registers that are used to save values across the
   // instruction (e.g., for saving state register values).

diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 20fbfa3619c2d90ec3d6163af87bba5b371206a0..e87f6a2215a8c6c637fb01b9e2571d73323156f7 100644 (file)
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -637,7 +637,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
     case MachineOperand::MO_CCRegister:
     case MachineOperand::MO_MachineRegister:
       {
-        int regNum = (int)mop.getAllocatedRegNum();
+        int regNum = (int)mop.getReg();
         
         if (regNum == Target.getRegInfo().getInvalidRegNum()) {
           // better to print code with NULL registers than to die

diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index 753f5d30f3d7fe5eeead3f0bb5d3b6bdd9c3d9d5..0db45e3e833a814d5b31155b572da2a494efd1b4 100644 (file)
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -661,7 +661,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
     // This is necessary because the Sparc backend doesn't actually lay out
     // registers in the real fashion -- it skips those that it chooses not to
     // allocate, i.e. those that are the FP, SP, etc.
-    unsigned fakeReg = MO.getAllocatedRegNum();
+    unsigned fakeReg = MO.getReg();
     unsigned realRegByClass = getRealRegNum(fakeReg, MI);
     DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
                     << realRegByClass << " (LLC: " 

diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index a69171c604ef8cfa9f691fb4e26c6931daa62ce9..d8a5515c72ddc48979d81440b5955760bb35e4e8 100644 (file)
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -63,16 +63,15 @@ DeleteInstruction(MachineBasicBlock& mvec,
 static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
   if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
     return (// both operands are allocated to the same register
-            MI->getOperand(0).getAllocatedRegNum() == 
-            MI->getOperand(1).getAllocatedRegNum());
+            MI->getOperand(0).getReg() ==  MI->getOperand(1).getReg());
   } else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
              MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
     unsigned srcWithDestReg;
     
     for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
       if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
-          MI->getOperand(srcWithDestReg).getAllocatedRegNum()
-          == MI->getOperand(2).getAllocatedRegNum())
+          MI->getOperand(srcWithDestReg).getReg()
+          == MI->getOperand(2).getReg())
         break;
     
     if (srcWithDestReg == 2)
@@ -82,7 +81,7 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
       unsigned otherOp = 1 - srcWithDestReg;
       return (// either operand otherOp is register %g0
               (MI->getOperand(otherOp).hasAllocatedReg() &&
-               MI->getOperand(otherOp).getAllocatedRegNum() ==
+               MI->getOperand(otherOp).getReg() ==
                target.getRegInfo().getZeroRegNum()) ||
               
               // or operand otherOp == 0

diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 5033a0aaa003539d08dd7c41ad18ad6df961fcf5..8d6e6d5ad7246d005f679dd0087c669d5be19f18 100644 (file)
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -52,7 +52,7 @@ SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
 // getZeroRegNum - returns the register that contains always zero.
 // this is the unified register number
 //
-int SparcRegInfo::getZeroRegNum() const {
+unsigned SparcRegInfo::getZeroRegNum() const {
   return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
                           SparcIntRegClass::g0);
 }

diff --git a/lib/Target/SparcV9/SparcV9RegInfo.h b/lib/Target/SparcV9/SparcV9RegInfo.h
index 34069d82f12827c968e46ae69a8c1c78e8ded3d6..3dd9e683e034723b523ced400eadf14965538e7e 100644 (file)
--- a/lib/Target/SparcV9/SparcV9RegInfo.h
+++ b/lib/Target/SparcV9/SparcV9RegInfo.h
@@ -86,7 +86,7 @@ public:
   // getZeroRegNum - returns the register that contains always zero this is the
   // unified register number
   //
-  virtual int getZeroRegNum() const;
+  virtual unsigned getZeroRegNum() const;
 
   // getCallAddressReg - returns the reg used for pushing the address when a
   // function is called. This can be used for other purposes between calls

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 298af02d8aec2752d12d4e1c9ec35488cf881d2d..b10d23e9e7d09268d328d9cd4448c2e8cef0d459 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -61,8 +61,8 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
              "invalid register-register move instruction");
-      sourceReg = MI.getOperand(1).getAllocatedRegNum();
-      destReg = MI.getOperand(0).getAllocatedRegNum();
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
       return true;
   }
   return false;