Rely on instruction format to determine so_reg operand for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56181 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 7abb7d2418b91bbb754321720bd67ba430e3e48d..1484d165e45400faf52c4ecd5ab611a7f2135ee2 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -372,7 +372,11 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
   }
 
   // Encode shifter operand.
-  if (TID.getNumOperands() - OpIdx > 1)
+  bool HasSoReg = (Format == ARMII::DPRdSoReg ||
+                   Format == ARMII::DPRnSoReg ||
+                   Format == ARMII::DPRSoReg  ||
+                   Format == ARMII::DPRSoRegS);
+  if (HasSoReg)
     // Encode SoReg.
     return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);