ARM: rockchip: correct L2 latency setting

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index bbc3462b07f561c2d08250d05b05ee522bcda20b..1f3572540becf509dff039764e4989f36b879886 100755 (executable)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -69,7 +69,7 @@
                cache-unified;
                cache-level = <2>;
                arm,tag-latency = <1 1 1>;
-               arm,data-latency = <2 3 1>;
+               arm,data-latency = <3 1 2>;
                rockchip,prefetch-ctrl = <0x70000003>;
                /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
                rockchip,power-ctrl = <0x3>;