Teach the code generator to use cvtss2sd as extload f32 -> f64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28131 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7186fe51afcb68e01cfb7c45ce2d26780c15fe2a..0ec11ac98f610efb63cda981036e3e5acfb7250a 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -207,10 +207,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     addRegisterClass(MVT::f32, X86::FR32RegisterClass);
     addRegisterClass(MVT::f64, X86::FR64RegisterClass);
 
-    // SSE has no load+extend ops
-    setOperationAction(ISD::EXTLOAD,  MVT::f32, Expand);
-    setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
-
     // Use ANDPD to simulate FABS.
     setOperationAction(ISD::FABS , MVT::f64, Custom);
     setOperationAction(ISD::FABS , MVT::f32, Custom);

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 6b799945b9d9fc93dad6bd02313533fd57f54ff4..3c1db6714621fa785b504562692aadd2c9918e82 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -526,7 +526,7 @@ def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
                 Requires<[HasSSE2]>;
 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
                  "cvtss2sd {$src, $dst|$dst, $src}",
-                 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
+                 [(set FR64:$dst, (extload addr:$src, f32))]>, XS,
                 Requires<[HasSSE2]>;
 
 // Match intrinsics which expect XMM operand(s).