--- /dev/null
+//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
+//
+// This file implements the LiveVariable analysis pass.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/CFG.h"
+#include "Support/DepthFirstIterator.h"
+
+static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
+
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+ const BasicBlock *BB) {
+ const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
+ MachineBasicBlock *MBB = Info.first;
+ unsigned BBNum = Info.second;
+
+ // Check to see if this basic block is one of the killing blocks. If so,
+ // remove it...
+ for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
+ if (VRInfo.Kills[i].first == MBB) {
+ VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
+ break;
+ }
+
+ if (MBB == VRInfo.DefBlock) return; // Terminate recursion
+
+ if (VRInfo.AliveBlocks.size() <= BBNum)
+ VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
+
+ if (VRInfo.AliveBlocks[BBNum])
+ return; // We already know the block is live
+
+ // Mark the variable known alive in this bb
+ VRInfo.AliveBlocks[BBNum] = true;
+
+ for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
+ MarkVirtRegAliveInBlock(VRInfo, *PI);
+}
+
+void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
+ MachineInstr *MI) {
+ // Check to see if this basic block is already a kill block...
+ if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
+ // Yes, this register is killed in this basic block already. Increase the
+ // live range by updating the kill instruction.
+ VRInfo.Kills.back().second = MI;
+ return;
+ }
+
+#ifndef NDEBUG
+ for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
+ assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
+#endif
+
+ assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
+
+ // Add a new kill entry for this basic block.
+ VRInfo.Kills.push_back(std::make_pair(MBB, MI));
+
+ // Update all dominating blocks to mark them known live.
+ const BasicBlock *BB = MBB->getBasicBlock();
+ for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
+ PI != E; ++PI)
+ MarkVirtRegAliveInBlock(VRInfo, *PI);
+}
+
+void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
+ if (PhysRegInfo[Reg]) {
+ PhysRegInfo[Reg] = MI;
+ PhysRegUsed[Reg] = true;
+ } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
+ for (; unsigned NReg = AliasSet[0]; ++AliasSet)
+ if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
+ PhysRegInfo[NReg] = MI;
+ PhysRegUsed[NReg] = true;
+ }
+ }
+}
+
+void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
+ // Does this kill a previous version of this register?
+ if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
+ if (PhysRegUsed[Reg])
+ RegistersKilled.insert(std::make_pair(LastUse, Reg));
+ else
+ RegistersDead.insert(std::make_pair(LastUse, Reg));
+ } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
+ for (; unsigned NReg = AliasSet[0]; ++AliasSet)
+ if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
+ if (PhysRegUsed[NReg])
+ RegistersKilled.insert(std::make_pair(LastUse, NReg));
+ else
+ RegistersDead.insert(std::make_pair(LastUse, NReg));
+ PhysRegInfo[NReg] = 0; // Kill the aliased register
+ }
+ }
+ PhysRegInfo[Reg] = MI;
+ PhysRegUsed[Reg] = false;
+}
+
+bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
+ // Build BBMap...
+ unsigned BBNum = 0;
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+ BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
+
+ // PhysRegInfo - Keep track of which instruction was the last use of a
+ // physical register. This is a purely local property, because all physical
+ // register references as presumed dead across basic blocks.
+ //
+ MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
+ bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
+ std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
+ (MachineInstr*)0);
+ PhysRegInfo = PhysRegInfoA;
+ PhysRegUsed = PhysRegUsedA;
+
+ const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
+ RegInfo = MF.getTarget().getRegisterInfo();
+
+ /// Get some space for a respectable number of registers...
+ VirtRegInfo.resize(64);
+
+ // Calculate live variable information in depth first order on the CFG of the
+ // function. This guarantees that we will see the definition of a virtual
+ // register before its uses due to dominance properties of SSA (except for PHI
+ // nodes, which are treated as a special case).
+ //
+ const BasicBlock *Entry = MF.getFunction()->begin();
+ for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
+ DFI != E; ++DFI) {
+ const BasicBlock *BB = *DFI;
+ std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
+ MachineBasicBlock *MBB = BBRec.first;
+ unsigned BBNum = BBRec.second;
+
+ // Loop over all of the instructions, processing them.
+ for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
+ I != E; ++I) {
+ MachineInstr *MI = *I;
+ const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
+
+ // Process all of the operands of the instruction...
+ unsigned NumOperandsToProcess = MI->getNumOperands();
+
+ // Unless it is a PHI node. In this case, ONLY process the DEF, not any
+ // of the uses. They will be handled in other basic blocks.
+ if (MI->getOpcode() == TargetInstrInfo::PHI)
+ NumOperandsToProcess = 1;
+
+ // Loop over implicit uses, using them.
+ if (const unsigned *ImplicitUses = MID.ImplicitUses)
+ for (unsigned i = 0; ImplicitUses[i]; ++i)
+ HandlePhysRegUse(ImplicitUses[i], MI);
+
+ // Process all explicit uses...
+ for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.opIsUse() || MO.opIsDefAndUse()) {
+ if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
+ unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
+ HandleVirtRegUse(getVarInfo(RegIdx), MBB, MI);
+ } else if (MO.isPhysicalRegister() && MO.getReg() != 0
+ /// FIXME: This is a gross hack, due to us not being able to
+ /// say that some registers are defined on entry to the
+ /// function. 5 = ESP
+&& MO.getReg() != 5
+) {
+ HandlePhysRegUse(MO.getReg(), MI);
+ }
+ }
+ }
+
+ // Loop over implicit defs, defining them.
+ if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
+ for (unsigned i = 0; ImplicitDefs[i]; ++i)
+ HandlePhysRegDef(ImplicitDefs[i], MI);
+
+ // Process all explicit defs...
+ for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.opIsDef() || MO.opIsDefAndUse()) {
+ if (MO.isVirtualRegister()) {
+ unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
+ VarInfo &VRInfo = getVarInfo(RegIdx);
+
+ assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
+ VRInfo.DefBlock = MBB; // Created here...
+ VRInfo.DefInst = MI;
+ VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
+ } else if (MO.isPhysicalRegister() && MO.getReg() != 0
+ /// FIXME: This is a gross hack, due to us not being able to
+ /// say that some registers are defined on entry to the
+ /// function. 5 = ESP
+&& MO.getReg() != 5
+) {
+ HandlePhysRegDef(MO.getReg(), MI);
+ }
+ }
+ }
+ }
+
+ // Handle any virtual assignments from PHI nodes which might be at the
+ // bottom of this basic block. We check all of our successor blocks to see
+ // if they have PHI nodes, and if so, we simulate an assignment at the end
+ // of the current block.
+ for (succ_const_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I){
+ MachineBasicBlock *Succ = BBMap.find(*I)->second.first;
+
+ // PHI nodes are guaranteed to be at the top of the block...
+ for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
+ I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
+ for (unsigned i = 1; ; i += 2)
+ if ((*I)->getOperand(i+1).getMachineBasicBlock() == MBB) {
+ MachineOperand &MO = (*I)->getOperand(i);
+ if (!MO.getVRegValueOrNull()) {
+ unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
+ VarInfo &VRInfo = getVarInfo(RegIdx);
+
+ // Only mark it alive only in the block we are representing...
+ MarkVirtRegAliveInBlock(VRInfo, BB);
+ break; // Found the PHI entry for this block...
+ }
+ }
+ }
+ }
+
+ // Loop over PhysRegInfo, killing any registers that are available at the
+ // end of the basic block. This also resets the PhysRegInfo map.
+ for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i)
+ if (PhysRegInfo[i])
+ HandlePhysRegDef(i, 0);
+ }
+
+ BBMap.clear();
+
+ // Convert the information we have gathered into VirtRegInfo and transform it
+ // into a form usable by RegistersKilled.
+ //
+ for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
+ for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
+ if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
+ RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
+ i + MRegisterInfo::FirstVirtualRegister));
+
+ else
+ RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
+ i + MRegisterInfo::FirstVirtualRegister));
+ }
+
+ return false;
+}
--- /dev/null
+//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
+//
+// This pass eliminates machine instruction PHI nodes by inserting copy
+// instructions. This destroys SSA information, but is the desired input for
+// some register allocators.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+namespace {
+ struct PNE : public MachineFunctionPass {
+ bool runOnMachineFunction(MachineFunction &Fn) {
+ bool Changed = false;
+
+ // Eliminate PHI instructions by inserting copies into predecessor blocks.
+ //
+ for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ Changed |= EliminatePHINodes(Fn, *I);
+
+ //std::cerr << "AFTER PHI NODE ELIM:\n";
+ //Fn.dump();
+ return Changed;
+ }
+
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addPreserved<LiveVariables>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ private:
+ /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
+ /// in predecessor basic blocks.
+ ///
+ bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
+ };
+
+ RegisterPass<PNE> X("phi-node-elimination",
+ "Eliminate PHI nodes for register allocation");
+}
+
+const PassInfo *PHIEliminationID = X.getPassInfo();
+
+/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
+/// predecessor basic blocks.
+///
+bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
+ if (MBB.front()->getOpcode() != TargetInstrInfo::PHI)
+ return false; // Quick exit for normal case...
+
+ LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
+ const TargetInstrInfo &MII = MF.getTarget().getInstrInfo();
+ const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
+
+ while (MBB.front()->getOpcode() == TargetInstrInfo::PHI) {
+ MachineInstr *MI = MBB.front();
+ // Unlink the PHI node from the basic block... but don't delete the PHI yet
+ MBB.erase(MBB.begin());
+
+ assert(MI->getOperand(0).isVirtualRegister() &&
+ "PHI node doesn't write virt reg?");
+
+ unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
+
+ // Create a new register for the incoming PHI arguments
+ const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
+ unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
+
+ // Insert a register to register copy in the top of the current block (by
+ // after any remaining phi nodes) which copies the new incoming register
+ // into the phi node destination.
+ //
+ MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
+ while ((*AfterPHIsIt)->getOpcode() == TargetInstrInfo::PHI) ++AfterPHIsIt;
+ RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
+
+ // Add information to LiveVariables to know that the incoming value is dead
+ if (LV) LV->addVirtualRegisterKill(IncomingReg, *(AfterPHIsIt-1));
+
+ // Now loop over all of the incoming arguments turning them into copies into
+ // the IncomingReg register in the corresponding predecessor basic block.
+ //
+ for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
+ MachineOperand &opVal = MI->getOperand(i-1);
+
+ // Get the MachineBasicBlock equivalent of the BasicBlock that is the
+ // source path the phi
+ MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
+
+ // Check to make sure we haven't already emitted the copy for this block.
+ // This can happen because PHI nodes may have multiple entries for the
+ // same basic block. It doesn't matter which entry we use though, because
+ // all incoming values are guaranteed to be the same for a particular bb.
+ //
+ // Note that this is N^2 in the number of phi node entries, but since the
+ // # of entries is tiny, this is not a problem.
+ //
+ bool HaveNotEmitted = true;
+ for (int op = MI->getNumOperands() - 1; op != i; op -= 2)
+ if (&opBlock == MI->getOperand(op).getMachineBasicBlock()) {
+ HaveNotEmitted = false;
+ break;
+ }
+
+ if (HaveNotEmitted) {
+ MachineBasicBlock::iterator I = opBlock.end()-1;
+
+ // must backtrack over ALL the branches in the previous block
+ while (MII.isTerminatorInstr((*I)->getOpcode()) && I != opBlock.begin())
+ --I;
+
+ // move back to the first branch instruction so new instructions
+ // are inserted right in front of it and not in front of a non-branch
+ if (!MII.isTerminatorInstr((*I)->getOpcode()))
+ ++I;
+
+ assert(opVal.isVirtualRegister() &&
+ "Machine PHI Operands must all be virtual registers!");
+ RegInfo->copyRegToReg(opBlock, I, IncomingReg, opVal.getReg(), RC);
+ }
+ }
+
+ // really delete the PHI instruction now!
+ delete MI;
+ }
+
+ return true;
+}
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