Make SPU backend handle insertelement and

store for "half vectors"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 9b8c2ddd06359fd2506f9eb4bba41522f6f2a004..e42417c64c68bc1c62374280703cc3504b236a50 100644 (file)
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -607,7 +607,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
     return true;
   } else if (Opc == ISD::Register 
            ||Opc == ISD::CopyFromReg 
-           ||Opc == ISD::UNDEF) {
+           ||Opc == ISD::UNDEF
+           ||Opc == ISD::Constant) {
     unsigned OpOpc = Op->getOpcode();
 
     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 3a945ceedbf7ef8d1950d72c01b61acf93ecb5f9..7a6bb0f6efe3a210c11c606611b943a4a188a6b2 100644 (file)
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2102,7 +2102,10 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
   SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
                                 DAG.getRegister(SPU::R1, PtrVT),
                                 DAG.getConstant(Idx, PtrVT));
-  SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
+  // widen the mask when dealing with half vectors
+  EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(), 
+                                128/ VT.getVectorElementType().getSizeInBits());
+  SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, maskVT, Pointer);
 
   SDValue result =
     DAG.getNode(SPUISD::SHUFB, dl, VT,

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 803ce567dc46f818529c7227da6323cb0070c40c..f1d08867180890986071777404a923b79219973d 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -63,6 +63,7 @@ let canFoldAsLoad = 1 in {
     def v2f64: LoadDFormVec<v2f64>;
 
     def v2i32: LoadDFormVec<v2i32>;
+    def v2f32: LoadDFormVec<v2f32>;
 
     def r128:  LoadDForm<GPRC>;
     def r64:   LoadDForm<R64C>;
@@ -97,6 +98,7 @@ let canFoldAsLoad = 1 in {
     def v2f64: LoadAFormVec<v2f64>;
 
     def v2i32: LoadAFormVec<v2i32>;
+    def v2f32: LoadAFormVec<v2f32>;
 
     def r128:  LoadAForm<GPRC>;
     def r64:   LoadAForm<R64C>;
@@ -131,6 +133,7 @@ let canFoldAsLoad = 1 in {
     def v2f64: LoadXFormVec<v2f64>;
 
     def v2i32: LoadXFormVec<v2i32>;
+    def v2f32: LoadXFormVec<v2f32>;
 
     def r128:  LoadXForm<GPRC>;
     def r64:   LoadXForm<R64C>;
@@ -181,6 +184,7 @@ multiclass StoreDForms
   def v2f64: StoreDFormVec<v2f64>;
 
   def v2i32: StoreDFormVec<v2i32>;
+  def v2f32: StoreDFormVec<v2f32>;
 
   def r128:  StoreDForm<GPRC>;
   def r64:   StoreDForm<R64C>;
@@ -213,6 +217,7 @@ multiclass StoreAForms
   def v2f64: StoreAFormVec<v2f64>;
 
   def v2i32: StoreAFormVec<v2i32>;
+  def v2f32: StoreAFormVec<v2f32>;
 
   def r128:  StoreAForm<GPRC>;
   def r64:   StoreAForm<R64C>;
@@ -247,6 +252,7 @@ multiclass StoreXForms
   def v2f64: StoreXFormVec<v2f64>;
 
   def v2i32: StoreXFormVec<v2i32>;
+  def v2f32: StoreXFormVec<v2f32>;
 
   def r128:  StoreXForm<GPRC>;
   def r64:   StoreXForm<R64C>;

diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll
index 004463a86d306a8bd0f294659c57b428cfc1cc46..b32c23b4280db57c8c9ddc771103bed7247b0d43 100644 (file)
--- a/test/CodeGen/CellSPU/v2f32.ll
+++ b/test/CodeGen/CellSPU/v2f32.ll
@@ -42,4 +42,22 @@ define %vec @test_splat(float %param ) {
   ret %vec %rv
 }
 
+define void @test_store(%vec %val, %vec* %ptr){
+
+;CHECK: stqd 
+  store %vec undef, %vec* null
+
+;CHECK: stqd $3, 0($4)
+;CHECK: bi $lr
+  store %vec %val, %vec* %ptr
+  ret void
+}
+
+define %vec @test_insert(){
+;CHECK: cwd
+;CHECK: shufb $3
+  %rv = insertelement %vec undef, float 0.0e+00, i32 undef
+;CHECK: bi $lr
+  ret %vec %rv
+}
 

diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll
index be3822a8d0c45398bb8f3b39427e8c942d5683f8..ca8af6ae74219eca1fadf91e4fa9ac4a1583be72 100644 (file)
--- a/test/CodeGen/CellSPU/v2i32.ll
+++ b/test/CodeGen/CellSPU/v2i32.ll
@@ -55,3 +55,10 @@ define i32 @test_extract() {
   ret i32 %rv
 }
 
+define void @test_store( %vec %val, %vec* %ptr)
+{
+;CHECK: stqd $3, 0($4)
+;CHECK: bi $lr
+  store %vec %val, %vec* %ptr
+  ret void
+}