Add ISD::ADD to MaskedValueIsZero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23685 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 60bb6c6795d1617da78516c31cd0bd3c67b5f3c8..f15ce5784c6c23b62f6bfa348d78d87f1cc2d8ea 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -215,6 +215,14 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
       return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
     }
     return false;
+  case ISD::ADD:
+    // (add X, Y) & C == 0 iff (X&C)&(Y&C) == 0 and all bits are low bits.
+    if ((Mask&(Mask+1)) == 0) {  // All low bits
+      if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
+          MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
+        return true;
+    }
+    break;
   case ISD::SUB:
     if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits