ARM: tegra: PL310 restore dynamic clock gating on resume

Tegra 2.6.36 code needs to restore PL310 dynamic clock gating upon
resume from a power event.

As of 2.6.39 the PL310 is re-init'ed from scratch upon resume,
and this patch can be dropped.

Change-Id: I8c1fb1add3c3cfcffff58fab642b84d8d5a7a90a
Signed-off-by: Todd Poynor <toddpoynor@google.com>

diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index 91d787f2adcb17d01545c85b7fe34ce7cb45cf54..1ca815d0fab8b38edae3b615cfaae188881a2070 100644 (file)
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -536,6 +536,8 @@ ENTRY(__cortex_a9_l2x0_restart)
        str     r6, [r9, #L2X0_DATA_LATENCY_CTRL]
        str     r7, [r9, #L2X0_PREFETCH_OFFSET]
        str     r4, [r9, #L2X0_AUX_CTRL]
+       mov     r4, #0x2                @ L2X0_DYNAMIC_CLK_GATING_EN
+       str     r4, [r9, #L2X0_PWR_CTRL]
        cmp     r0, #0
 
        beq     __reenable_l2x0