Add VLD1-lane testcases for quad-register types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117975 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index 57e74dfe2498bc7e4244caaaf87e177c691e07dc..d6ff6b9f298ddc358e06c0b0d06c691459a21c1b 100644 (file)
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -27,6 +27,33 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
         ret <2 x i32> %tmp3
 }
 
+define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
+;CHECK: vld1laneQi8:
+;CHECK: vld1.8 {d17[1]}, [r0]
+       %tmp1 = load <16 x i8>* %B
+       %tmp2 = load i8* %A, align 1
+       %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
+       ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vld1laneQi16:
+;CHECK: vld1.16 {d17[1]}, [r0]
+       %tmp1 = load <8 x i16>* %B
+       %tmp2 = load i16* %A, align 2
+       %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
+       ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vld1laneQi32:
+;CHECK: vld1.32 {d17[1]}, [r0]
+       %tmp1 = load <4 x i32>* %B
+       %tmp2 = load i32* %A, align 4
+       %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
+       ret <4 x i32> %tmp3
+}
+
 %struct.__neon_int8x8x2_t = type { <8 x i8>,  <8 x i8> }
 %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
 %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }