Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21

as the "Permanently UNDEFINED" instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95873 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index eb7d4e40446984dfb5c76071391830a4ef7f6c56..1e3847fcfde83f1b79e9d9434b9c1adc16ae9243 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -619,6 +619,16 @@ def DBG : AI<(outs), (ins i32imm:$opt), Pseudo, NoItinerary, "dbg", "\t$opt",
   let Inst{7-4} = 0b1111;
 }
 
+// A5.4 Permanently UNDEFINED instructions.
+def TRAP : AI<(outs), (ins), Pseudo, NoItinerary, "trap", "",
+              [/* For disassembly only; pattern left blank */]>,
+           Requires<[IsARM]> {
+  let Inst{27-25} = 0b011;
+  let Inst{24-20} = 0b11111;
+  let Inst{7-5} = 0b111;
+  let Inst{4} = 0b1;
+}
+
 // Address computation and loads and stores in PIC mode.
 let isNotDuplicable = 1 in {
 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),