//===----------------------------------------------------------------------===//
#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/MC/MCFixupKindInfo.h"
using namespace llvm;
{ "FK_SecRel_8", 0, 64, 0 }
};
- assert((size_t)Kind <= sizeof(Builtins) / sizeof(Builtins[0]) &&
- "Unknown fixup kind");
+ assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind");
return Builtins[Kind];
}
static const int IntSigs[] = {
SIGHUP, SIGINT, SIGPIPE, SIGTERM, SIGUSR1, SIGUSR2
};
-static const int *const IntSigsEnd =
- IntSigs + sizeof(IntSigs) / sizeof(IntSigs[0]);
+static const int *const IntSigsEnd = array_endof(IntSigs);
// KillSigs - Signals that represent that we have a bug, and our prompt
// termination has been ordered.
, SIGEMT
#endif
};
-static const int *const KillSigsEnd =
- KillSigs + sizeof(KillSigs) / sizeof(KillSigs[0]);
+static const int *const KillSigsEnd = array_endof(KillSigs);
static unsigned NumRegisteredSignals = 0;
static struct {
static void RegisterHandler(int Signal) {
- assert(NumRegisteredSignals <
- sizeof(RegisteredSignalInfo)/sizeof(RegisteredSignalInfo[0]) &&
+ assert(NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) &&
"Out of space for signal handlers!");
struct sigaction NewHandler;
return true;
// Then compare against the list of ancient reserved names
- for (size_t i = 0; i < sizeof(sReservedNames) / sizeof(const char *); ++i) {
+ for (size_t i = 0; i < array_lengthof(sReservedNames); ++i) {
if (path.equals_lower(sReservedNames[i]))
return true;
}
lastRegToSaveIndex = REnd - ARM::R0;
} else {
firstRegToSaveIndex = CCInfo.getFirstUnallocated
- (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
+ (GPRArgRegs, array_lengthof(GPRArgRegs));
lastRegToSaveIndex = 4;
}
// FIXME: This is a total hack, finish mc'izing the PPC backend.
if (OutStreamer.hasRawTextSupport()) {
- assert(Directive < sizeof(CPUDirectives) / sizeof(*CPUDirectives) &&
+ assert(Directive < array_lengthof(CPUDirectives) &&
"CPUDirectives[] might not be up-to-date!");
OutStreamer.EmitRawText("\t.machine " + Twine(CPUDirectives[Directive]));
}
(int)MVT::v2i32,
(int)MVT::v4i32
};
- size_t NumTypes = sizeof(types) / sizeof(*types);
+ const size_t NumTypes = array_lengthof(types);
for (unsigned int x = 0; x < NumTypes; ++x) {
MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
(int)MVT::v2f64,
(int)MVT::v2i64
};
- size_t NumTypes = sizeof(types) / sizeof(*types);
- size_t NumFloatTypes = sizeof(FloatTypes) / sizeof(*FloatTypes);
- size_t NumIntTypes = sizeof(IntTypes) / sizeof(*IntTypes);
- size_t NumVectorTypes = sizeof(VectorTypes) / sizeof(*VectorTypes);
+ const size_t NumTypes = array_lengthof(types);
+ const size_t NumFloatTypes = array_lengthof(FloatTypes);
+ const size_t NumIntTypes = array_lengthof(IntTypes);
+ const size_t NumVectorTypes = array_lengthof(VectorTypes);
const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
// These are the current register classes that are
//===----------------------------------------------------------------------===//
#include "InstCombine.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
}
}
- assert((NextTmpIdx <= sizeof(TmpResult)/sizeof(TmpResult[0]) + 1) &&
+ assert((NextTmpIdx <= array_lengthof(TmpResult) + 1) &&
"out-of-bound access");
if (ConstAdd)