struct MachineFunctionAnalysis : public FunctionPass {
private:
const TargetMachine &TM;
- CodeGenOpt::Level OptLevel;
MachineFunction *MF;
unsigned NextFnNum;
public:
static char ID;
- explicit MachineFunctionAnalysis(const TargetMachine &tm,
- CodeGenOpt::Level OL = CodeGenOpt::Default);
+ explicit MachineFunctionAnalysis(const TargetMachine &tm);
~MachineFunctionAnalysis();
MachineFunction &getMF() const { return *MF; }
- CodeGenOpt::Level getOptLevel() const { return OptLevel; }
virtual const char* getPassName() const {
return "Machine Function Analysis";
///
CodeModel::Model CMModel;
+ /// OptLevel - Optimization level.
+ ///
+ CodeGenOpt::Level OptLevel;
+
public:
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
- CodeModel::Model CM = CodeModel::Default);
+ CodeModel::Model CM = CodeModel::Default,
+ CodeGenOpt::Level OL = CodeGenOpt::Default);
Reloc::Model getRelocationModel() const { return RelocationModel; }
CodeModel::Model getCodeModel() const { return CMModel; }
+
+ CodeGenOpt::Level getOptLevel() const { return OptLevel; }
};
} // namespace llvm
enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
}
+ // Code generation optimization level.
+ namespace CodeGenOpt {
+ enum Level {
+ None, // -O0
+ Less, // -O1
+ Default, // -O2, -Os
+ Aggressive // -O3
+ };
+ }
+
} // end llvm namespace
#endif
StringRef TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
Reloc::Model RM,
- CodeModel::Model CM);
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
StringRef CPU,
StringRef Features,
Reloc::Model RM,
- CodeModel::Model CM);
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer);
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT);
/// registered.
MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
- /// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo,
- /// if registered.
+ /// MCCodeGenInfoCtorFn - Constructor function for this target's
+ /// MCCodeGenInfo, if registered.
MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;
/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
///
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
- CodeModel::Model CM) const {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) const {
if (!MCCodeGenInfoCtorFn)
return 0;
- return MCCodeGenInfoCtorFn(Triple, RM, CM);
+ return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
}
/// createMCInstrInfo - Create a MCInstrInfo implementation.
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
- StringRef Features,
- Reloc::Model RM = Reloc::Default,
- CodeModel::Model CM = CodeModel::Default) const {
+ StringRef Features,
+ Reloc::Model RM = Reloc::Default,
+ CodeModel::Model CM = CodeModel::Default,
+ CodeGenOpt::Level OL = CodeGenOpt::Default) const {
if (!TargetMachineCtorFn)
return 0;
- return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
+ return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM, OL);
}
/// createMCAsmBackend - Create a target specific assembly parser.
TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
}
private:
- static MCCodeGenInfo *Allocator(StringRef TT,
- Reloc::Model RM, CodeModel::Model CM) {
+ static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model RM,
+ CodeModel::Model CM, CodeGenOpt::Level OL) {
return new MCCodeGenInfoImpl();
}
};
static TargetMachine *Allocator(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM,
- CodeModel::Model CM) {
- return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
+ return new TargetMachineImpl(T, TT, CPU, FS, RM, CM, OL);
}
};
class formatted_raw_ostream;
class raw_ostream;
-// Code generation optimization level.
-namespace CodeGenOpt {
- enum Level {
- None, // -O0
- Less, // -O1
- Default, // -O2, -Os
- Aggressive // -O3
- };
-}
-
namespace Sched {
enum Preference {
None, // No preference
/// medium, large, and target default.
CodeModel::Model getCodeModel() const;
+ /// getOptLevel - Returns the optimization level: None, Less,
+ /// Default, or Aggressive.
+ CodeGenOpt::Level getOptLevel() const;
+
/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
///
static bool getAsmVerbosityDefault();
virtual bool addPassesToEmitFile(PassManagerBase &,
formatted_raw_ostream &,
CodeGenFileType,
- CodeGenOpt::Level,
bool = true) {
return true;
}
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
JITCodeEmitter &,
- CodeGenOpt::Level,
bool = true) {
return true;
}
virtual bool addPassesToEmitMC(PassManagerBase &,
MCContext *&,
raw_ostream &,
- CodeGenOpt::Level,
bool = true) {
return true;
}
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
///
- bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+ bool addCommonCodeGenPasses(PassManagerBase &,
bool DisableVerify, MCContext *&OutCtx);
public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
- /// generation. If OptLevel is None, the code generator should emit code as
- /// fast as possible, though the generated code may be less efficient.
+ /// generation.
virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level,
bool DisableVerify = true);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &MCE,
- CodeGenOpt::Level,
bool DisableVerify = true);
/// addPassesToEmitMC - Add passes to the specified pass manager to get
virtual bool addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx,
raw_ostream &OS,
- CodeGenOpt::Level OptLevel,
bool DisableVerify = true);
/// Target-Independent Code Generator Pass Configuration Options.
/// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
/// passes (which are run just before instruction selector).
- virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addPreISel(PassManagerBase &) {
return true;
}
/// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions.
- virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addInstSelector(PassManagerBase &) {
return true;
}
/// addPreRegAlloc - This method may be implemented by targets that want to
/// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
- virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addPreRegAlloc(PassManagerBase &) {
return false;
}
/// to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
- virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addPostRegAlloc(PassManagerBase &) {
return false;
}
/// run passes after prolog-epilog insertion and before the second instruction
/// scheduling pass. This should return true if -print-machineinstrs should
/// print after these passes.
- virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addPreSched2(PassManagerBase &) {
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
+ virtual bool addPreEmitPass(PassManagerBase &) {
return false;
}
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned.
- virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
+ virtual bool addCodeEmitter(PassManagerBase &,
JITCodeEmitter &) {
return true;
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS) {
- CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
+ CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
AsmInfo = T.createMCAsmInfo(Triple);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
MCContext *Context = 0;
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true;
assert(Context != 0 && "Failed to get MCContext");
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
MCContext *Ctx = 0;
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
- addCodeEmitter(PM, OptLevel, JCE);
+ addCodeEmitter(PM, JCE);
PM.add(createGCInfoDeleter());
return false; // success!
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx,
raw_ostream &Out,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
if (hasMCSaveTempLabels())
/// emitting to assembly files or machine code output.
///
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
bool DisableVerify,
MCContext *&OutContext) {
// Standard LLVM-Level Passes.
PM.add(createVerifierPass());
// Run loop strength reduction before anything else.
- if (OptLevel != CodeGenOpt::None && !DisableLSR) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
break;
}
- if (OptLevel != CodeGenOpt::None && !DisableCGP)
+ if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
- addPreISel(PM, OptLevel);
+ addPreISel(PM);
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on.
- PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+ PM.add(new MachineFunctionAnalysis(*this));
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
- (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
+ (getOptLevel() == CodeGenOpt::None &&
+ EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
// Ask the target for an isel.
- if (addInstSelector(PM, OptLevel))
+ if (addInstSelector(PM))
return true;
// Print the instruction selected machine code...
PM.add(createExpandISelPseudosPass());
// Pre-ra tail duplication.
- if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
}
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
- if (OptLevel != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass());
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
PM.add(createLocalStackSlotAllocationPass());
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
}
// Run pre-ra passes.
- if (addPreRegAlloc(PM, OptLevel))
+ if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes");
// Perform register allocation.
- PM.add(createRegisterAllocator(OptLevel));
+ PM.add(createRegisterAllocator(getOptLevel()));
printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
if (!DisableSSC)
}
// Run post-ra passes.
- if (addPostRegAlloc(PM, OptLevel))
+ if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass());
printAndVerify(PM, "After PrologEpilogCodeInserter");
// Run pre-sched2 passes.
- if (addPreSched2(PM, OptLevel))
+ if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
- PM.add(createPostRAScheduler(OptLevel));
+ if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
+ PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler");
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding");
}
// Tail duplication.
- if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate");
}
if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs()));
- if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
if (EnableBlockPlacement) {
// MachineBlockPlacement is an experimental pass which is disabled by
// default currently. Eventually it should subsume CodePlacementOpt, so
}
}
- if (addPreEmitPass(PM, OptLevel))
+ if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes");
return false;
char MachineFunctionAnalysis::ID = 0;
-MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm,
- CodeGenOpt::Level OL) :
- FunctionPass(ID), TM(tm), OptLevel(OL), MF(0) {
+MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm) :
+ FunctionPass(ID), TM(tm), MF(0) {
initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
}
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
- if (TM->addPassesToEmitMC(PM, Ctx, OS, CodeGenOpt::Default, false)) {
+ if (TM->addPassesToEmitMC(PM, Ctx, OS, false)) {
report_fatal_error("Target does not support MC emission!");
}
#include "llvm/MC/MCCodeGenInfo.h"
using namespace llvm;
-void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) {
+void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
RelocationModel = RM;
CMModel = CM;
+ OptLevel = OL;
}
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS),
JITInfo(),
InstrItins(Subtarget.getInstrItineraryData()) {
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), InstrInfo(Subtarget),
DataLayout(Subtarget.isAPCS_ABI() ?
std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32-S32") :
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL),
InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
}
-bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- if (OptLevel != CodeGenOpt::None && EnableGlobalMerge)
+bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) {
+ if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
PM.add(createGlobalMergePass(getTargetLowering()));
return false;
}
-bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- PM.add(createARMISelDag(*this, OptLevel));
+bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) {
+ PM.add(createARMISelDag(*this, getOptLevel()));
return false;
}
-bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
- if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+ if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true));
- if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
+ if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9())
PM.add(createMLxExpansionPass());
return true;
}
-bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass());
if (Subtarget.hasNEON())
// proper scheduling.
PM.add(createARMExpandPseudoPass());
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
}
return true;
}
-bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) {
if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
PM.add(createThumb2SizeReductionPass());
}
bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
// Machine code emitter pass for ARM.
PM.add(createARMJITCodeEmitterPass(*this, JCE));
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
}
// Pass Pipeline Configuration
- virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
- JITCodeEmitter &MCE);
+ virtual bool addPreISel(PassManagerBase &PM);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreRegAlloc(PassManagerBase &PM);
+ virtual bool addPreSched2(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
+ virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
};
/// ARMTargetMachine - ARM target machine.
public:
ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const ARMRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
public:
ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
}
static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
Triple TheTriple(TT);
// Default relocation model on Darwin is PIC, not DynamicNoPIC.
RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
}
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
bool CTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &o,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
if (FileType != TargetMachine::CGFT_AssemblyFile) return true;
struct CTargetMachine : public TargetMachine {
CTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify);
virtual const TargetData *getTargetData() const { return 0; }
}
static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// For the time being, use static relocations, since there's really no
// support for PIC yet.
- X->InitMCCodeGenInfo(Reloc::Static, CM);
+ X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
return X;
}
SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS),
DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this),
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool SPUTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool SPUTargetMachine::addInstSelector(PassManagerBase &PM) {
// Install an instruction selector.
PM.add(createSPUISelDag(*this));
return false;
// passes to run just before printing the assembly
bool SPUTargetMachine::
-addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPreEmitPass(PassManagerBase &PM) {
// load the TCE instruction scheduler, if available via
// loaded plugins
typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
public:
SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
/// Return the subtarget implementation object
virtual const SPUSubtarget *getSubtargetImpl() const {
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &);
};
} // end namespace llvm
bool CPPTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &o,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
if (FileType != TargetMachine::CGFT_AssemblyFile) return true;
PM.add(new CppWriter(o));
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify);
virtual const TargetData *getTargetData() const { return 0; }
MBlazeTargetMachine::
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM):
- LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL):
+ LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this),
// Install an instruction selector pass using
// the ISelDag to gen MBlaze code.
-bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM) {
PM.add(createMBlazeISelDag(*this));
return false;
}
// Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
-bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM) {
PM.add(createMBlazeDelaySlotFillerPass(*this));
return true;
}
public:
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level Opt);
- virtual bool addPreEmitPass(PassManagerBase &PM,CodeGenOpt::Level Opt);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
};
} // End llvm namespace
}
static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::Static;
if (CM == CodeModel::Default)
CM = CodeModel::Small;
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
}
static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
StringRef TT,
StringRef CPU,
StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS),
// FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
FrameLowering(Subtarget) { }
-bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM) {
// Install an instruction selector.
- PM.add(createMSP430ISelDag(*this, OptLevel));
+ PM.add(createMSP430ISelDag(*this, getOptLevel()));
return false;
}
-bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM) {
// Must run branch selection immediately preceding the asm printer.
PM.add(createMSP430BranchSelectionPass());
return false;
public:
MSP430TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;
return &TSInfo;
}
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
}; // MSP430TargetMachine.
} // end namespace llvm
}
static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::PIC_;
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool isLittle):
- LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ?
(Subtarget.isABI_N64() ?
MipsebTargetMachine::
MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM) :
- MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL) :
+ MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
MipselTargetMachine::
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM) :
- MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL) :
+ MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
Mips64ebTargetMachine::
Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM) :
- MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL) :
+ MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
Mips64elTargetMachine::
Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM) :
- MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL) :
+ MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
+addInstSelector(PassManagerBase &PM)
{
PM.add(createMipsISelDag(*this));
return false;
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
+addPreEmitPass(PassManagerBase &PM)
{
PM.add(createMipsDelaySlotFillerPass(*this));
return true;
}
bool MipsTargetMachine::
-addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPreRegAlloc(PassManagerBase &PM) {
// Do not restore $gp if target is Mips64.
// In N32/64, $gp is a callee-saved register.
if (!Subtarget.hasMips64())
}
bool MipsTargetMachine::
-addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPostRegAlloc(PassManagerBase &PM) {
PM.add(createMipsExpandPseudoPass(*this));
return true;
}
bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- JITCodeEmitter &JCE) {
+ JITCodeEmitter &JCE) {
// Machine code emitter pass for Mips.
PM.add(createMipsJITCodeEmitterPass(*this, JCE));
return false;
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool isLittle);
virtual const MipsInstrInfo *getInstrInfo() const
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
+ virtual bool addPreRegAlloc(PassManagerBase &PM);
+ virtual bool addPostRegAlloc(PassManagerBase &);
virtual bool addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE);
};
public:
MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// MipselTargetMachine - Mips32 little endian target machine.
public:
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// Mips64ebTargetMachine - Mips64 big endian target machine.
public:
Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// Mips64elTargetMachine - Mips64 little endian target machine.
public:
Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
} // End llvm namespace
}
static MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
PTXTargetMachine::PTXTargetMachine(const Target &T,
StringRef TT, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64Bit)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
DataLayout(is64Bit ? DataLayout64 : DataLayout32),
Subtarget(TT, CPU, FS, is64Bit),
FrameLowering(Subtarget),
PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
}
PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
}
-bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- PM.add(createPTXISelDag(*this, OptLevel));
+bool PTXTargetMachine::addInstSelector(PassManagerBase &PM) {
+ PM.add(createPTXISelDag(*this, getOptLevel()));
return false;
}
-bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
// PTXMFInfoExtract must after register allocation!
- //PM.add(createPTXMFInfoExtract(*this, OptLevel));
+ //PM.add(createPTXMFInfoExtract(*this));
return false;
}
bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// This is mostly based on LLVMTargetMachine::addPassesToEmitFile
// Add common CodeGen passes.
MCContext *Context = 0;
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true;
assert(Context != 0 && "Failed to get MCContext");
}
bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
bool DisableVerify,
MCContext *&OutContext) {
// Add standard LLVM codegen passes.
PM.add(createVerifierPass());
// Run loop strength reduction before anything else.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
//PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
// The lower invoke pass may create unreachable code. Remove it.
PM.add(createUnreachableBlockEliminationPass());
- if (OptLevel != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
- addPreISel(PM, OptLevel);
+ addPreISel(PM);
//PM.add(createPrintFunctionPass("\n\n"
// "*** Final LLVM Code input to ISel ***\n",
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on.
- PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+ PM.add(new MachineFunctionAnalysis(*this));
// Ask the target for an isel.
- if (addInstSelector(PM, OptLevel))
+ if (addInstSelector(PM))
return true;
// Print the instruction selected machine code...
PM.add(createExpandISelPseudosPass());
// Pre-ra tail duplication.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
}
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
- if (OptLevel != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass());
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
PM.add(createLocalStackSlotAllocationPass());
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
}
// Run pre-ra passes.
- if (addPreRegAlloc(PM, OptLevel))
+ if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes");
// Perform register allocation.
printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
PM.add(createStackSlotColoringPass(false));
}
// Run post-ra passes.
- if (addPostRegAlloc(PM, OptLevel))
+ if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass());
printAndVerify(PM, "After PrologEpilogCodeInserter");
// Run pre-sched2 passes.
- if (addPreSched2(PM, OptLevel))
+ if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None) {
- PM.add(createPostRAScheduler(OptLevel));
+ if (getOptLevel() != CodeGenOpt::None) {
+ PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler");
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding");
}
// Tail duplication.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate");
}
//if (PrintGCInfo)
// PM.add(createGCInfoPrinter(dbgs()));
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
PM.add(createCodePlacementOptPass());
printNoVerify(PM, "After CodePlacementOpt");
}
- if (addPreEmitPass(PM, OptLevel))
+ if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes");
- PM.add(createPTXMFInfoExtract(*this, OptLevel));
- PM.add(createPTXFPRoundingModePass(*this, OptLevel));
+ PM.add(createPTXMFInfoExtract(*this, getOptLevel()));
+ PM.add(createPTXFPRoundingModePass(*this, getOptLevel()));
return false;
}
PTXTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64Bit);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
- virtual bool addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPostRegAlloc(PassManagerBase &PM);
// We override this method to supply our own set of codegen passes.
virtual bool addPassesToEmitFile(PassManagerBase &,
formatted_raw_ostream &,
CodeGenFileType,
- CodeGenOpt::Level,
bool = true);
// Emission of machine code through JITCodeEmitter is not supported.
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
JITCodeEmitter &,
- CodeGenOpt::Level,
bool = true) {
return true;
}
virtual bool addPassesToEmitMC(PassManagerBase &,
MCContext *&,
raw_ostream &,
- CodeGenOpt::Level,
bool = true) {
return true;
}
private:
- bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+ bool addCommonCodeGenPasses(PassManagerBase &,
bool DisableVerify, MCContext *&OutCtx);
}; // class PTXTargetMachine
PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
}; // class PTX32TargetMachine
class PTX64TargetMachine : public PTXTargetMachine {
PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
}; // class PTX32TargetMachine
} // namespace llvm
}
static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
else
RM = Reloc::Static;
}
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64Bit)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
}
PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
}
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
// Install an instruction selector.
PM.add(createPPCISelDag(*this));
return false;
}
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
// Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
// FIXME: This should be moved to TargetJITInfo!!
if (Subtarget.isPPC64())
public:
PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM, bool is64Bit);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const {
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
+ virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE);
virtual bool getEnableTailMergeDefault() const;
};
public:
PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// PPC64TargetMachine - PowerPC 64-bit target machine.
public:
PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
} // end namespace llvm
}
static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64bit)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
FrameLowering(Subtarget) {
}
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
PM.add(createSparcISelDag(*this));
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this));
return true;
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM,
- CodeModel::Model CM)
- : SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
}
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM,
- CodeModel::Model CM)
- : SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
}
public:
SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM, bool is64bit);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
};
/// SparcV8TargetMachine - Sparc 32-bit target machine
public:
SparcV8TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// SparcV9TargetMachine - Sparc 64-bit target machine
public:
SparcV9TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
} // end namespace llvm
return CodeGenInfo->getCodeModel();
}
+/// getOptLevel - Returns the optimization level: None, Less,
+/// Default, or Aggressive.
+CodeGenOpt::Level TargetMachine::getOptLevel() const {
+ if (!CodeGenInfo)
+ return CodeGenOpt::Default;
+ return CodeGenInfo->getOptLevel();
+}
+
bool TargetMachine::getAsmVerbosityDefault() {
return AsmVerbosityDefault;
}
}
static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
Triple T(TT);
// 64-bit JIT places everything in the same buffer except external funcs.
CM = is64Bit ? CodeModel::Large : CodeModel::Small;
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, false),
DataLayout(getSubtargetImpl()->isTargetDarwin() ?
"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
"n8:16:32-S128" :
X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, true),
DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
"n8:16:32:64-S128"),
InstrInfo(*this),
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64Bit)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
// Install an instruction selector.
- PM.add(createX86ISelDag(*this, OptLevel));
+ PM.add(createX86ISelDag(*this, getOptLevel()));
// For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!Subtarget.is64Bit())
return false;
}
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
PM.add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
-bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
bool ShouldPrint = false;
- if (OptLevel != CodeGenOpt::None && Subtarget.hasXMMInt()) {
+ if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
}
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
PM.add(createX86JITCodeEmitterPass(*this, JCE));
X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
bool is64Bit);
virtual const X86InstrInfo *getInstrInfo() const {
}
// Set up the pass pipeline.
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
- virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM);
+ virtual bool addPreRegAlloc(PassManagerBase &PM);
+ virtual bool addPostRegAlloc(PassManagerBase &PM);
+ virtual bool addPreEmitPass(PassManagerBase &PM);
+ virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE);
};
public:
X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
public:
X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
}
static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
- CodeModel::Model CM) {
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- X->InitMCCodeGenInfo(RM, CM);
+ X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
- : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS),
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),
TSInfo(*this) {
}
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM) {
PM.add(createXCoreISelDag(*this));
return false;
}
public:
XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM);
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const XCoreFrameLowering *getFrameLowering() const {
virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addInstSelector(PassManagerBase &PM);
};
} // end namespace llvm
FeaturesStr = Features.getString();
}
+ CodeGenOpt::Level OLvl = CodeGenOpt::Default;
+ switch (OptLevel) {
+ default:
+ errs() << argv[0] << ": invalid optimization level.\n";
+ return 1;
+ case ' ': break;
+ case '0': OLvl = CodeGenOpt::None; break;
+ case '1': OLvl = CodeGenOpt::Less; break;
+ case '2': OLvl = CodeGenOpt::Default; break;
+ case '3': OLvl = CodeGenOpt::Aggressive; break;
+ }
+
std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr,
- RelocModel, CMModel));
+ RelocModel, CMModel, OLvl));
assert(target.get() && "Could not allocate target machine!");
TargetMachine &Target = *target.get();
(GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0]));
if (!Out) return 1;
- CodeGenOpt::Level OLvl = CodeGenOpt::Default;
- switch (OptLevel) {
- default:
- errs() << argv[0] << ": invalid optimization level.\n";
- return 1;
- case ' ': break;
- case '0': OLvl = CodeGenOpt::None; break;
- case '1': OLvl = CodeGenOpt::Less; break;
- case '2': OLvl = CodeGenOpt::Default; break;
- case '3': OLvl = CodeGenOpt::Aggressive; break;
- }
-
// Build up all of the passes that we want to do to the module.
PassManager PM;
formatted_raw_ostream FOS(Out->os());
// Ask the target to add backend passes as necessary.
- if (Target.addPassesToEmitFile(PM, FOS, FileType, OLvl, NoVerify)) {
+ if (Target.addPassesToEmitFile(PM, FOS, FileType, NoVerify)) {
errs() << argv[0] << ": target does not support generation of this"
<< " file type!\n";
return 1;
projects / oota-llvm.git / commitdiff