Add support to convert more 64-bit instructions to 3-address instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42642 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 08ae6d374b28080ad3be134b4a4b271370b7104c..951c8dc53a0cbf0ad09b03b7b14c93bc957b2ced 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -277,39 +277,54 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
 
   if (!hasLiveCondCodeDef(MI))
   switch (MI->getOpcode()) {
+  case X86::INC64r:
   case X86::INC32r:
-  case X86::INC64_32r:
+  case X86::INC64_32r: {
     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
-    NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
+    unsigned Opc = MI->getOpcode() == X86::INC64r ? X86::LEA64r : X86::LEA32r;
+    NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
     break;
+  }
   case X86::INC16r:
   case X86::INC64_16r:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
     NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
     break;
+  case X86::DEC64r:
   case X86::DEC32r:
-  case X86::DEC64_32r:
+  case X86::DEC64_32r: {
     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
-    NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
+    unsigned Opc = MI->getOpcode() == X86::DEC64r ? X86::LEA64r : X86::LEA32r;
+    NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
     break;
+  }
   case X86::DEC16r:
   case X86::DEC64_16r:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
     NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
     break;
-  case X86::ADD32rr:
+  case X86::ADD64rr:
+  case X86::ADD32rr: {
     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
-    NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
-                     MI->getOperand(2).getReg());
+    unsigned Opc = MI->getOpcode() == X86::ADD64rr ? X86::LEA64r : X86::LEA32r;
+    NewMI = addRegReg(BuildMI(get(Opc), Dest), Src, MI->getOperand(2).getReg());
     break;
+  }
   case X86::ADD16rr:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
     NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
                      MI->getOperand(2).getReg());
     break;
+  case X86::ADD64ri32:
+  case X86::ADD64ri8:
+    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
+    if (MI->getOperand(2).isImmediate())
+      NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
+                          MI->getOperand(2).getImmedValue());
+    break;
   case X86::ADD32ri:
   case X86::ADD32ri8:
     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
@@ -328,6 +343,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
   case X86::SHL16ri:
     if (DisableLEA16) return 0;
   case X86::SHL32ri:
+  case X86::SHL64ri: 
     assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
            "Unknown shl instruction!");
     unsigned ShAmt = MI->getOperand(2).getImmedValue();
@@ -335,7 +351,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
       X86AddressMode AM;
       AM.Scale = 1 << ShAmt;
       AM.IndexReg = Src;
-      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
+      unsigned Opc = MI->getOpcode() == X86::SHL64ri ? X86::LEA64r
+        : (MI->getOpcode() == X86::SHL32ri ? X86::LEA32r : X86::LEA16r);
       NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
     }
     break;

diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index 71a2d94ccf75ae5abc884be523adfb021139d9c5..a6369b86f09c0d24c5580979128128c3e3579eb1 100644 (file)
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -454,6 +454,7 @@ let Uses = [CL] in
 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
                   "shl{q}\t{%cl, $dst|$dst, %CL}",
                   [(set GR64:$dst, (shl GR64:$src, CL))]>;
+let isConvertibleToThreeAddress = 1 in   // Can transform into LEA.
 def SHL64ri  : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
                     "shl{q}\t{$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;