let Inst{5} = 0;
}
+// Preload signals the memory system of possible future data/instruction access.
+// These are for disassembly only.
+multiclass APreLoad<bit data, bit read, string opc> {
+
+ def i : AXI<(outs), (ins GPR:$base, i32imm:$imm), MiscFrm, NoItinerary,
+ !strconcat(opc, "\t[$base, $imm]"), []> {
+ let Inst{31-26} = 0b111101;
+ let Inst{25} = 0; // 0 for immediate form
+ let Inst{24} = data;
+ let Inst{22} = read;
+ let Inst{21-20} = 0b01;
+ }
+
+ def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
+ !strconcat(opc, "\t$addr"), []> {
+ let Inst{31-26} = 0b111101;
+ let Inst{25} = 1; // 1 for register form
+ let Inst{24} = data;
+ let Inst{22} = read;
+ let Inst{21-20} = 0b01;
+ let Inst{4} = 0;
+ }
+}
+
+defm PLD : APreLoad<1, 1, "pld">;
+defm PLDW : APreLoad<1, 0, "pldw">;
+defm PLI : APreLoad<0, 1, "pli">;
+
def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM]> {
"mov", "\t$dst, $src, rrx",
[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
-//===----------------------------------------------------------------------===//
-// Shift Instructions.
-//
-// These are for disassembly only. See also MOVs above.
-
-class AShI<string opc, bits<2> type>
- : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src, am3offset:$offset), LdMiscFrm,
- IIC_iMOVsr, opc, "\t$dst, $src, $offset", []>, UnaryDP {
- let Inst{6-5} = type;
- let Inst{25} = 0;
-}
-
-def LSL : AShI<"lsl", 0b00>;
-def LSR : AShI<"lsr", 0b01>;
-def ASR : AShI<"asr", 0b10>;
-def ROR : AShI<"ror", 0b11>;
-
-def RRX : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), LdMiscFrm, IIC_iMOVsr,
- "rrx", "\t$dst, $src", []>, UnaryDP {
- let Inst{25} = 0;
- let Inst{11-7} = 0b00000;
- let Inst{6-4} = 0b110;
-}
-
// These aren't really mov instructions, but we have to define them this way
// due to flag operands.