bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index cb3d923351fa24c6bc795a7fb6042a7c26c3600f..50ac5e9c69df1891f6d370512b400ff1d3fc1cb5 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -555,10 +555,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
     CallOpc = (isDirect || Subtarget->hasV5TOps())
       ? ARMISD::CALL : ARMISD::CALL_NOLINK;
   }
-  if (CallOpc == ARMISD::CALL_NOLINK) {
-    // On CALL_NOLINK we must move PC to LR
+  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
+    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
     Chain = DAG.getCopyToReg(Chain, ARM::LR,
-                             DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
     InFlag = Chain.getValue(1);
   }
 

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 201f65c7f5a7f4923b9e83bcf63d8267e866df1d..36d2e4a0460fa8f37f3a6b5bf1a8d68585f9cbb5 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -370,6 +370,8 @@ class AI3<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AI4<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AIx2<dag ops, string asm, list<dag> pattern>
+  : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
 class AI1x2<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -546,9 +548,9 @@ let isCall = 1, noResults = 1,
                [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AI<(ops GPR:$dst, variable_ops),
-                "bx $dst",
-                [(ARMcall_nolink GPR:$dst)]>;
+    def BX : AIx2<(ops GPR:$dst, variable_ops),
+                  "mov lr, pc\n\tbx $dst",
+                  [(ARMcall_nolink GPR:$dst)]>;
   }
 }
 

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index a1f03bd1726a77ce27cebea80913e4bc9bcbad64..3c7cd03ee75c9952b764cda135d0266ddfb98acd 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -189,12 +189,10 @@ let isCall = 1, noResults = 1,
   def tBLXr : TI<(ops GPR:$dst, variable_ops),
                   "blx $dst",
                   [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
-  let Uses = [LR] in {
-    // ARMv4T
-    def tBX : TI<(ops GPR:$dst, variable_ops),
-                  "bx $dst",
+  // ARMv4T
+  def tBX : TIx2<(ops GPR:$dst, variable_ops),
+                  "cpy lr, pc\n\tbx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
-  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {