#define SysSrv_DdrMode (RK30_CPU_AXI_BUS_BASE+0x10)
#define SysSrv_ReadLatency (RK30_CPU_AXI_BUS_BASE+0x14)
+#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3066B)
+#define SRAM_SIZE RK30_IMEM_SIZE
+#elif defined(CONFIG_ARCH_RK3188)
+#define SRAM_SIZE RK3188_IMEM_SIZE
+#endif
+
#define ddr_print(x...) printk( "DDR DEBUG: " x )
/***********************************
isb();
DDR_SAVE_SP(save_sp);
- for(i=0;i<16;i++)
+ for(i=0;i<SRAM_SIZE/4096;i++)
{
n=temp[1024*i];
barrier();
isb();
DDR_SAVE_SP(save_sp);
-#if defined(CONFIG_ARCH_RK30)
-#define SRAM_SIZE RK30_IMEM_SIZE
-#elif defined(CONFIG_ARCH_RK3188)
-#define SRAM_SIZE RK3188_IMEM_SIZE
-#endif
for(i=0;i<SRAM_SIZE/4096;i++)
{
n=temp[1024*i];
outer_flush_all();
//flush_tlb_all();
-#if defined(CONFIG_ARCH_RK30)
-#define SRAM_SIZE RK30_IMEM_SIZE
-#elif defined(CONFIG_ARCH_RK3188)
-#define SRAM_SIZE RK3188_IMEM_SIZE
-#endif
for(i=0;i<SRAM_SIZE/4096;i++)
{
n=temp[1024*i];
uint32_t die=1;
uint32_t gsr,dqstr;
- ddr_print("version 1.00 201300814 \n");
+ ddr_print("version 1.00 20131106 \n");
mem_type = pPHY_Reg->DCR.b.DDRMD;
ddr_speed_bin = dram_speed_bin;