reg test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21914 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
new file mode 100644 (file)
index 0000000..55dbcbf
--- /dev/null
+++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -0,0 +1,14 @@
+; llvm-as < %s | llc -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'mov %EDX, 1'
+
+; check that fastcc is passing stuff in regs.
+
+declare fastcc long %callee(long)
+
+long %caller() {
+       %X = call fastcc long %callee(long 4294967299)  ;; (1ULL << 32) + 3
+       ret long %X
+}
+
+fastcc long %caller2(long %X) {
+       ret long %X
+}