--- /dev/null
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include "pm.h"
+//#include "sram.h"
+
+
+struct rkpm_sram_ops DEFINE_PIE_DATA(pm_sram_ops);
+//for sram
+static __sramdata u32 rkpm_sram_ctrbits;
+
+/****************** for pm.c and in sram***************************************/
+//only usr in sram function
+#define rkpm_chk_sram_ctrbit(bit) (rkpm_sram_ctrbits&(bit))
+#define rkpm_chk_sram_ctrbits(bits) (rkpm_sram_ctrbits&(bits))
+
+#define RKPM_SRAM_FUN(fun) \
+ if(DATA(pm_sram_ops).fun)\
+ (DATA(pm_sram_ops).fun)()
+
+#define RKPM_BITCTR_SRAM_FUN(ctr,fun) \
+ if(rkpm_chk_sram_ctrbit(RKPM_CTR_##ctr)&&DATA(pm_sram_ops).fun)\
+ (DATA(pm_sram_ops).fun)()
+
+// fun with paramater
+#define RKPM_BITSCTR_SRAM_PFUN(bits,fun,fun_p) \
+ if(rkpm_chk_sram_ctrbits(bits)&&DATA(pm_sram_ops).fun_p) \
+ {DATA(pm_sram_ops).fun;} while(0)
+
+/********************************sram print**********************************/
+
+void PIE_FUNC(rkpm_sram_printch_pie)(char byte)
+{
+ if(DATA(pm_sram_ops).printch)
+ DATA(pm_sram_ops).printch(byte);
+
+ if (byte == '\n')
+ FUNC(rkpm_sram_printch_pie)('\r');
+}
+
+void PIE_FUNC(rkpm_sram_printhex_pie)(unsigned int hex)
+{
+ int i = 8;
+ FUNC(rkpm_sram_printch_pie)('0');
+ FUNC(rkpm_sram_printch_pie)('x');
+ while (i--) {
+ unsigned char c = (hex & 0xF0000000) >> 28;
+ FUNC(rkpm_sram_printch_pie)(c < 0xa ? c + '0' : c - 0xa + 'a');
+ hex <<= 4;
+ }
+}
+
+
+/******************************************pm main function******************************************/
+#define RKPM_CTR_SYSCLK RKPM_OR_3BITS(SYSCLK_DIV,SYSCLK_32K,SYSCLK_OSC_DIS)
+
+void __sramfunc rkpm_sram_suspend(u32 ctrbits)
+{
+
+ rkpm_sram_printch('5');
+ RKPM_BITCTR_SRAM_FUN(DDR,ddr);
+
+ rkpm_sram_printch('6');
+ RKPM_BITCTR_SRAM_FUN(VOLTS,volts);
+
+ rkpm_sram_printch('7');
+
+ RKPM_BITCTR_SRAM_FUN(GTCLKS,gtclks);
+
+ RKPM_BITSCTR_SRAM_PFUN(RKPM_CTR_SYSCLK,sysclk(rkpm_sram_ctrbits),sysclk);
+
+ RKPM_BITCTR_SRAM_FUN(PMIC,pmic);
+
+ // if(rkpm_chk_sram_ctrbit(RKPM_CTR_SRAM_NO_WFI))
+ {
+ dsb();
+ wfi();
+ }
+
+ RKPM_BITCTR_SRAM_FUN(PMIC,re_pmic);
+
+ RKPM_BITSCTR_SRAM_PFUN(RKPM_CTR_SYSCLK,re_sysclk(rkpm_sram_ctrbits),re_sysclk);
+
+ RKPM_BITCTR_SRAM_FUN(GTCLKS,re_gtclks);
+
+ rkpm_sram_printch('7');
+ RKPM_BITCTR_SRAM_FUN(VOLTS,re_volts);
+
+ rkpm_sram_printch('6');
+ RKPM_BITCTR_SRAM_FUN(DDR,re_ddr);
+
+ rkpm_sram_printch('5');
+}
+
+void PIE_FUNC(rkpm_sram_suspend_arg)(void *arg)
+{
+ rkpm_sram_ctrbits=*((u32 *)arg);
+
+ // rkpm_sram_printhex(rkpm_sram_ctrbits);
+ //rkpm_sram_printhex(*((u32 *)arg));
+ rkpm_sram_suspend(rkpm_sram_ctrbits);
+
+
+}
+void rkpm_pie_init(void)
+{
+ rkpm_set_pie_info(kern_to_pie(rockchip_pie_chunk, &DATA(pm_sram_ops))
+ ,fn_to_pie(rockchip_pie_chunk, &FUNC(rkpm_sram_suspend_arg)));
+}
+#include <linux/kernel.h>
+#include <linux/init.h>
#include <linux/suspend.h>
+#include "pm.h"
-static int rockchip_suspend_enter(suspend_state_t state)
+
+static struct rkpm_ops pm_ops={NULL};
+
+static struct rkpm_sram_ops *p_pm_sram_ops=NULL;//pie point for pm_sram_ops
+static rkpm_sram_suspend_arg_cb p_suspend_pie_cb=NULL;
+
+// for user setting
+static u32 rkpm_ctrbits=0;
+//for judging rkpm_ctrbits valid ,save ifself
+static u32 rkpm_jdg_ctrbits=0;
+static u32 rkpm_jdg_sram_ctrbits=0;
+
+/**************************************ddr callback setting***************************************/
+
+void rkpm_set_pie_info(struct rkpm_sram_ops *pm_sram_ops,rkpm_sram_suspend_arg_cb pie_cb)
+{
+
+ p_pm_sram_ops=pm_sram_ops;
+ p_suspend_pie_cb=pie_cb;
+
+
+}
+
+
+void rkpm_set_ops_prepare_finish(rkpm_ops_void_callback prepare,rkpm_ops_void_callback finish)
+{
+ pm_ops.prepare=prepare;
+ pm_ops.finish=finish;
+}
+
+void rkpm_set_ops_pwr_dmns(rkpm_ops_void_callback pwr_dmns,rkpm_ops_void_callback re_pwr_dmns)
+{
+ pm_ops.pwr_dmns=pwr_dmns;
+ pm_ops.re_pwr_dmns=re_pwr_dmns;
+}
+
+void rkpm_set_ops_gtclks(rkpm_ops_void_callback gtclks,rkpm_ops_void_callback re_gtclks)
+{
+ pm_ops.gtclks=gtclks;
+ pm_ops.re_gtclks=re_gtclks;
+}
+
+
+void rkpm_set_ops_plls(rkpm_ops_void_callback plls,rkpm_ops_void_callback re_plls)
+{
+ pm_ops.plls=plls;
+ pm_ops.re_plls=re_plls;
+}
+
+
+void rkpm_set_ops_gpios(rkpm_ops_void_callback gpios,rkpm_ops_void_callback re_gpios)
+{
+ pm_ops.gpios=gpios;
+ pm_ops.re_gpios=re_gpios;
+}
+void rkpm_set_ops_printch(rkpm_ops_printch_callback printch)
+{
+ pm_ops.printch=printch;
+}
+
+void rkpm_set_ops_regs_pread(rkpm_ops_void_callback regs_pread)
+{
+ pm_ops.regs_pread=regs_pread;
+}
+
+
+
+/**************************************sram callback setting***************************************/
+void rkpm_set_sram_ops_volt(rkpm_ops_void_callback volts,rkpm_ops_void_callback re_volts)
+{
+ if(p_pm_sram_ops)
+ {
+ p_pm_sram_ops->volts=volts;
+ p_pm_sram_ops->re_volts=re_volts;
+ }
+}
+
+void rkpm_set_sram_ops_gtclks(rkpm_ops_void_callback gtclks,rkpm_ops_void_callback re_gtclks)
+{
+ if(p_pm_sram_ops)
+ {
+ p_pm_sram_ops->gtclks=gtclks;
+ p_pm_sram_ops->re_gtclks=re_gtclks;
+ }
+}
+
+void rkpm_set_sram_ops_sysclk(rkpm_ops_paramter_u32_cb sysclk,rkpm_ops_paramter_u32_cb re_sysclk)
+{
+ if(p_pm_sram_ops)
+ {
+ p_pm_sram_ops->sysclk=sysclk;
+ p_pm_sram_ops->re_sysclk=re_sysclk;
+ }
+}
+
+void rkpm_set_sram_ops_pmic(rkpm_ops_void_callback pmic,rkpm_ops_void_callback re_pmic)
+{
+ if(p_pm_sram_ops)
+ {
+ p_pm_sram_ops->pmic=pmic;
+ p_pm_sram_ops->re_pmic=re_pmic;
+ }
+}
+
+void rkpm_set_sram_ops_ddr(rkpm_ops_void_callback ddr,rkpm_ops_void_callback re_ddr)
+{
+ if(p_pm_sram_ops)
+ {
+ p_pm_sram_ops->ddr=ddr;
+ p_pm_sram_ops->re_ddr=re_ddr;
+ }
+}
+void rkpm_set_sram_ops_printch(rkpm_ops_printch_callback printch)
+{
+ if(p_pm_sram_ops)
+ p_pm_sram_ops->printch=printch;
+}
+
+/******************for user ************************/
+void inline rkpm_set_ctrbits(u32 bits)
+{
+ rkpm_ctrbits = bits;
+
+}
+void inline rkpm_add_ctrbits(u32 bits)
+{
+ rkpm_ctrbits |= bits;
+
+}
+u32 inline rkpm_get_ctrbits(void)
+{
+ return rkpm_ctrbits;
+}
+void inline rkpm_add_ctrbit(int bit)
+{
+ rkpm_ctrbits|=bit;
+}
+u32 inline rkpm_chk_ctrbit(int bit)
+{
+ return (rkpm_ctrbits&bit);
+}
+
+//clear
+void inline rkpm_clr_ctrbit(int bit)
+{
+ rkpm_ctrbits&=~bit;
+}
+
+/****************** for pm.c************************/
+
+static void inline rkpm_set_jdg_ctrbits(u32 bits)
+{
+ rkpm_jdg_ctrbits = bits;
+
+}
+static u32 inline rkpm_get_jdg_ctrbits(void)
+{
+ return rkpm_jdg_ctrbits;
+}
+
+static void inline rkpm_add_jdg_ctrbit(int bit)
+{
+ rkpm_jdg_ctrbits|=bit;
+}
+
+static u32 inline rkpm_chk_jdg_ctrbit(int bit)
+{
+ return (rkpm_jdg_ctrbits&bit);
+}
+static u32 inline rkpm_chk_jdg_ctrbits(int bits)
+{
+ return (rkpm_jdg_ctrbits&bits);
+}
+//clear
+static void inline rkpm_clr_jdg_ctrbit(int bit)
+{
+ rkpm_jdg_ctrbits&=~bit;
+}
+
+
+#define RKPM_DDR_FUN(fun) \
+ if(pm_ops.fun)\
+ (pm_ops.fun)()
+
+
+#define RKPM_BITCTR_DDR_FUN(ctr,fun) \
+ if(rkpm_chk_jdg_ctrbit(RKPM_CTR_##ctr)&&pm_ops.fun)\
+ (pm_ops.fun)()
+
+
+
+void rkpm_ctrbits_prepare(void)
{
- cpu_do_idle();
+
+ //rkpm_sram_ctrbits=rkpm_ctrbits;
+
+ rkpm_jdg_ctrbits=rkpm_ctrbits;
+
+ //if plls is no pd,clk rate is high, volts can not setting low,so we need to judge ctrbits
+ if(rkpm_chk_jdg_ctrbit(RKPM_CTR_VOLTS))
+ {
+ rkpm_clr_jdg_ctrbit(RKPM_CTR_VOLTS);
+ }
+
+ rkpm_jdg_sram_ctrbits=rkpm_jdg_ctrbits;
+
+ //clk gating will gate ddr clk in sram
+ if(!rkpm_chk_val_ctrbit(rkpm_jdg_sram_ctrbits,RKPM_CTR_DDR))
+ {
+ // rkpm_clr_val_ctrbit(rkpm_jdg_sram_ctrbits,RKPM_CTR_GTCLKS);
+ }
+
+}
+
+struct rk_soc_pm_info_st {
+ int offset;
+ char *name;
+};
+
+#define RK_SOC_PM_HELP_(id,NAME)\
+ {\
+ .offset= RKPM_CTR_##id,\
+ .name= NAME,\
+ }
+
+struct rk_soc_pm_info_st rk_soc_pm_helps[]={
+#if 0
+ RK_SOC_PM_HELP_(NO_PD,"pd is not power dn"),
+ RK_SOC_PM_HELP_(NO_CLK_GATING,"clk is not gating"),
+ RK_SOC_PM_HELP_(NO_PLL,"pll is not power dn"),
+ RK_SOC_PM_HELP_(NO_VOLT,"volt is not set suspend"),
+ RK_SOC_PM_HELP_(NO_GPIO,"gpio is not control "),
+ //RK_SOC_PM_HELP_(NO_SRAM,"not enter sram code"),
+ RK_SOC_PM_HELP_(NO_DDR,"ddr is not reflash"),
+ RK_SOC_PM_HELP_(NO_PMIC,"pmic is not suspend"),
+ RK_SOC_PM_HELP_(RET_DIRT,"sys return from pm_enter directly"),
+ RK_SOC_PM_HELP_(SRAM_NO_WFI,"sys is not runing wfi in sram"),
+ RK_SOC_PM_HELP_(WAKE_UP_KEY,"send a power key to wake up lcd"),
+#endif
+};
+
+ssize_t rk_soc_pm_helps_sprintf(char *buf)
+{
+ char *s = buf;
+ int i;
+
+ for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
+ {
+ s += sprintf(s, "bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
+ }
+
+ return (s-buf);
+}
+
+void rk_soc_pm_helps_printk(void)
+{
+ int i;
+ printk("**************rkpm_ctr_bits bits help***********:\n");
+ for(i=0;i<ARRAY_SIZE(rk_soc_pm_helps);i++)
+ {
+ printk("bit(%d): %s\n", rk_soc_pm_helps[i].offset,rk_soc_pm_helps[i].name);
+ }
+}
+
+#if 0
+static int __init early_param_rk_soc_pm_ctr(char *str)
+{
+ get_option(&str, &rkpm_ctrbits);
+
+ printk("********rkpm_ctr_bits information is following:*********\n");
+ printk("rkpm_ctr_bits=%x\n",rkpm_ctrbits);
+ if(rkpm_ctrbits)
+ {
+ rk_soc_pm_helps_printk();
+ }
+ printk("********rkpm_ctr_bits information end*********\n");
+ return 0;
+}
+#endif
+
+/*******************************************log*********************************************/
+
+
+bool pm_log;
+
+extern void pm_emit_log_char(char c);
+
+/********************************ddr print**********************************/
+void rkpm_ddr_printch(char byte)
+{
+ if(pm_ops.printch)
+ pm_ops.printch(byte);
+
+ if (byte == '\n')
+ rkpm_ddr_printch('\r');
+}
+void rkpm_ddr_printascii(const char *s)
+{
+ while (*s) {
+ rkpm_ddr_printch(*s);
+ s++;
+ }
+}
+
+void rkpm_ddr_printhex(unsigned int hex)
+{
+ int i = 8;
+ rkpm_ddr_printch('0');
+ rkpm_ddr_printch('x');
+ while (i--) {
+ unsigned char c = (hex & 0xF0000000) >> 28;
+ rkpm_ddr_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
+ hex <<= 4;
+ }
+}
+
+inline int rkpm_dbgctr_enter(void)
+{
+ if(rkpm_chk_jdg_ctrbits(RKPM_OR_2BITS(RET_DIRT,ONLY_WFI)))
+ {
+ if(rkpm_chk_jdg_ctrbit(RKPM_CTR_ONLY_WFI))
+ {
+ local_fiq_disable();
+ dsb();
+ wfi();
+ local_fiq_enable();
+ }
+ return -1;
+ }
+ return 0;
+}
+void plls_resume(void);
+
+static int rkpm_enter(suspend_state_t state)
+{
+
+ printk("%s\n",__FUNCTION__);
+ printk(KERN_DEBUG "pm: ");
+
+ rkpm_ctrbits_prepare();
+
+ if(rkpm_dbgctr_enter())
+ return 0;
+
+ RKPM_DDR_FUN(prepare);
+
+
+ rkpm_ddr_printch('0');
+
+ RKPM_BITCTR_DDR_FUN(PWR_DMNS,pwr_dmns);
+
+ rkpm_ddr_printch('1');
+
+ local_fiq_disable();
+
+ RKPM_BITCTR_DDR_FUN(GTCLKS,gtclks);
+
+ rkpm_ddr_printch('2');
+
+ RKPM_BITCTR_DDR_FUN(PLLS,plls);
+
+ rkpm_ddr_printch('3');
+
+ RKPM_BITCTR_DDR_FUN(GPIOS,gpios);
+
+ RKPM_DDR_FUN(regs_pread);
+
+ rkpm_ddr_printch('4');
+
+ pm_log = false;
+
+ if(rkpm_chk_jdg_ctrbit(RKPM_CTR_NORIDLE_MD))
+ call_with_stack(p_suspend_pie_cb,&rkpm_jdg_sram_ctrbits, rockchip_sram_stack);
+ {
+ dsb();
+ wfi();
+ }
+
+ pm_log = true;
+
+ rkpm_ddr_printch('4');
+
+ RKPM_BITCTR_DDR_FUN(GPIOS,re_gpios);
+
+ rkpm_ddr_printch('3');
+
+ RKPM_BITCTR_DDR_FUN(PLLS,re_plls);
+
+ rkpm_ddr_printch('2');
+
+ RKPM_BITCTR_DDR_FUN(GTCLKS,re_gtclks);
+
+ local_fiq_enable();
+
+ rkpm_ddr_printch('1');
+
+ RKPM_BITCTR_DDR_FUN(PWR_DMNS,re_pwr_dmns);
+
+ rkpm_ddr_printch('0');
+
+ pm_log = false;
+
+ printk(KERN_CONT "\n");
+
+ rkpm_ddr_printch('\n');
+
+ RKPM_DDR_FUN(finish);
+ return 0;
+}
+
+int rkpm_enter_tst(void)
+{
+
+ return rkpm_enter(0);
+
+}
+
+static int rkpm_suspend_prepare(void)
+{
+ /* disable entering idle by disable_hlt() */
+ //disable_hlt();
return 0;
}
-static const struct platform_suspend_ops rockchip_suspend_ops = {
+static void rkpm_suspend_finish(void)
+{
+ //enable_hlt();
+
+ #if 0 //def CONFIG_KEYS_RK29
+ if(rkpm_check_ctrbits(1<<RKPM_CTR_WAKE_UP_KEY))
+ {
+ rk28_send_wakeup_key();
+ printk("rk30_pm_finish rk28_send_wakeup_key\n");
+ }
+ #endif
+}
+
+
+
+
+
+static struct platform_suspend_ops rockchip_suspend_ops = {
+ .enter = rkpm_enter,
.valid = suspend_valid_only_mem,
- .enter = rockchip_suspend_enter,
+ .prepare = rkpm_suspend_prepare,
+ .finish = rkpm_suspend_finish,
};
-
void __init rockchip_suspend_init(void)
{
- suspend_set_ops(&rockchip_suspend_ops);
+ printk("%s\n",__FUNCTION__);
+ suspend_set_ops(&rockchip_suspend_ops);
+ return;
}
+
+
--- /dev/null
+#ifndef __MACH_ROCKCHIP_PM1_H
+#define __MACH_ROCKCHIP_PM1_H
+
+#include <dt-bindings/suspend/rockchip-pm.h>
+
+
+
+
+#define RKPM_LOOPS_PER_USEC 24
+#define RKPM_LOOP(loops) do { unsigned int i = (loops); if (i < 7) i = 7; barrier(); asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i)); } while (0)
+/* delay on slow mode */
+#define rkpm_udelay(usecs) RKPM_LOOP((usecs)*RKPM_LOOPS_PER_USEC)
+/* delay on deep slow mode */
+#define rkpm_32k_udelay(usecs) RKPM_LOOP(((usecs)*RKPM_LOOPS_PER_USEC)/(24000000/32768))
+
+
+
+typedef void (*rkpm_ops_void_callback)(void);
+typedef void (*rkpm_ops_printch_callback)(char byte);
+typedef void (*rkpm_ops_paramter_u32_cb)(u32 val);
+typedef void (*rkpm_sram_suspend_arg_cb)(void *arg);
+
+// ops in ddr callback
+struct rkpm_ops {
+
+ rkpm_ops_void_callback prepare;
+ rkpm_ops_void_callback finish;
+ rkpm_ops_void_callback regs_pread;
+
+ rkpm_ops_void_callback pwr_dmns;
+ rkpm_ops_void_callback re_pwr_dmns;
+
+ rkpm_ops_void_callback gtclks;
+ rkpm_ops_void_callback re_gtclks;
+
+
+ rkpm_ops_void_callback plls;
+ rkpm_ops_void_callback re_plls;
+
+ rkpm_ops_void_callback gpios;
+ rkpm_ops_void_callback re_gpios;
+
+ rkpm_ops_printch_callback printch;
+
+};
+
+
+// ops in intmen callback
+struct rkpm_sram_ops{
+
+ rkpm_ops_void_callback volts;
+ rkpm_ops_void_callback re_volts;
+
+ rkpm_ops_void_callback gtclks;
+ rkpm_ops_void_callback re_gtclks;
+
+ rkpm_ops_paramter_u32_cb sysclk;
+ rkpm_ops_paramter_u32_cb re_sysclk;
+
+ rkpm_ops_void_callback pmic;
+ rkpm_ops_void_callback re_pmic;
+
+ rkpm_ops_void_callback ddr;
+ rkpm_ops_void_callback re_ddr;
+
+ rkpm_ops_printch_callback printch;
+};
+
+#if 0
+struct rkpm_gpios_info_st{
+ u32 pins;
+ u32 in_out;
+ u32 level_pull;
+};
+#endif
+
+/******************ctr bits setting ************************/
+#define rkpm_chk_val_ctrbit(val,bit) ((val)&(bit))//check bit
+#define rkpm_chk_val_ctrbits(val,bits) ((val)&(bits)) //check bits
+
+/*********************************pm control******************************************/
+extern void rkpm_set_pie_info(struct rkpm_sram_ops *pm_sram_ops,rkpm_sram_suspend_arg_cb pie_cb);
+extern void rkpm_set_ops_prepare_finish(rkpm_ops_void_callback prepare,rkpm_ops_void_callback finish);
+extern void rkpm_set_ops_pwr_dmns(rkpm_ops_void_callback pwr_dmns,rkpm_ops_void_callback re_pwr_dmns);
+extern void rkpm_set_ops_gtclks(rkpm_ops_void_callback gtclks,rkpm_ops_void_callback re_gtclks);
+extern void rkpm_set_ops_plls(rkpm_ops_void_callback plls,rkpm_ops_void_callback re_plls);
+extern void rkpm_set_ops_gpios(rkpm_ops_void_callback gpios,rkpm_ops_void_callback re_gpios);
+extern void rkpm_set_ops_printch(rkpm_ops_printch_callback printch);
+extern void rkpm_set_ops_regs_pread(rkpm_ops_void_callback regs_pread);
+
+
+extern void rkpm_pie_init(void);
+extern void rkpm_set_sram_ops_volt(rkpm_ops_void_callback volts,rkpm_ops_void_callback re_volts);
+extern void rkpm_set_sram_ops_gtclks(rkpm_ops_void_callback gtclks,rkpm_ops_void_callback re_gtclks);
+extern void rkpm_set_sram_ops_sysclk(rkpm_ops_paramter_u32_cb sysclk,rkpm_ops_paramter_u32_cb re_sysclk);
+extern void rkpm_set_sram_ops_pmic(rkpm_ops_void_callback pmic,rkpm_ops_void_callback re_pmic);
+extern void rkpm_set_sram_ops_ddr(rkpm_ops_void_callback ddr,rkpm_ops_void_callback re_ddr);
+extern void rkpm_set_sram_ops_printch(rkpm_ops_printch_callback printch);
+
+extern void inline rkpm_set_ctrbits(u32 bits);
+extern u32 inline rkpm_get_ctrbits(void);
+extern void inline rkpm_set_ctrbit(int idxs);
+extern u32 inline rkpm_get_ctrbit(int idxs);
+extern void inline rkpm_clr_ctrbit(int idxs);//clear
+
+extern void rkpm_ddr_printch(char byte);
+extern void rkpm_ddr_printascii(const char *s);
+extern void rkpm_ddr_printhex(unsigned int hex);
+
+extern u32 clk_suspend_clkgt_info_get(u32 *clk_ungt_msk,u32 *clk_gt_last_set,u32 buf_cnt);
+
+
+/********************************sram print**********************************/
+#include "sram.h"
+
+#if 1//def CPU
+extern void PIE_FUNC(rkpm_sram_printch_pie)(char byte);
+extern void PIE_FUNC(rkpm_sram_printhex_pie)(unsigned int hex);
+
+#define rkpm_sram_printch(byte) FUNC(rkpm_sram_printch_pie)(byte)
+//void __sramfunc rkpm_sram_printascii(const char *s);
+#define rkpm_sram_printhex(hex) FUNC(rkpm_sram_printhex_pie)(hex)
+#endif
+
+#endif
+
void rkclk_init_clks(struct device_node *node);
+static struct device_node * clk_root_node=NULL;
static void __init rk_clk_tree_init(struct device_node *np)
{
struct device_node *node, *node_tmp, *node_prd, *node_init;
struct rkclk *rkclk;
const char *compatible;
-
-
+
printk("%s start! cru base = 0x%08x\n", __func__, (u32)RK_CRU_VIRT);
node_init=of_find_node_by_name(NULL,"clocks-init");
clk_err("%s: can not get clocks-init node\n", __func__);
return;
}
+ clk_root_node=np;
for_each_available_child_of_node(np, node) {
clk_debug("\n");
cnt_parent = of_count_phandle_with_args(np,
"rockchip,clocks-init-parent", "#clock-init-cells");
- printk("%s: cnt_parent = %d\n",__FUNCTION__,cnt_parent);
+ clk_debug("%s: cnt_parent = %d\n",__FUNCTION__,cnt_parent);
for (i = 0; i < cnt_parent; i++) {
clk_parent_name=NULL;
cnt_rate = of_count_phandle_with_args(np, "rockchip,clocks-init-rate",
"#clock-init-cells");
- printk("%s: cnt_rate = %d\n",__FUNCTION__,cnt_rate);
+ clk_debug("%s: cnt_rate = %d\n",__FUNCTION__,cnt_rate);
for (i = 0; i < cnt_rate; i++) {
clk_name=of_clk_init_rate_get_info(np, i, &clk_rate);
clk_set_rate(clk_c, clk_rate);
- printk("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
+ clk_debug("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
clk_rate);
}
}
+u32 clk_suspend_clkgt_info_get(u32 *clk_ungt_msk,u32 *clk_ungt_msk_last,u32 buf_cnt)
+{
+
+ struct device_node *node,*node_gt;
+ u32 temp_val[2];
+ int gt_cnt;
+ int ret;
+ void __iomem *cru_base,*gt_base, *reg_n, *reg_p;
+
+ gt_cnt=0;
+ cru_base= of_iomap(clk_root_node, 0);
+
+ for_each_available_child_of_node(clk_root_node, node) {
+
+ if (of_device_is_compatible(node,"rockchip,rk-gate-cons"))
+ {
+
+ for_each_available_child_of_node(node, node_gt) {
+
+ if(gt_cnt>=buf_cnt)
+ {
+ clk_err("%s:save buf is overflow\n",__FUNCTION__);
+ return 0;
+ }
+
+ ret = of_property_read_u32_array(node_gt,"rockchip,suspend-clkgating-setting",temp_val,2);
+ if(!ret)
+ {
+ clk_ungt_msk[gt_cnt]=temp_val[0];
+ clk_ungt_msk_last[gt_cnt]=temp_val[1];
+ }
+ else
+ {
+ clk_ungt_msk[gt_cnt]=0xffff;
+ clk_ungt_msk_last[gt_cnt]=0xffff;
+ }
+
+ if(gt_cnt==0)
+ {
+ gt_base=of_iomap(node_gt, 0);
+ reg_p=gt_base;
+ reg_n=gt_base;
+ }
+ else
+ {
+ reg_n=of_iomap(node_gt, 0);
+
+ if(((u32)reg_n-(u32)reg_p)!=4)
+ {
+ printk("%s: gt reg is not continue\n",__FUNCTION__);
+ return 0;
+ }
+ reg_p=reg_n;
+ }
+
+ clk_debug("%s:gt%d,reg=%x,val=(%x,%x)\n",__FUNCTION__,gt_cnt,(u32)reg_n,
+ clk_ungt_msk[gt_cnt], clk_ungt_msk_last[gt_cnt]);
+
+ gt_cnt++;
+
+ }
+
+ break;
+ }
+ }
+
+ if(gt_cnt!=buf_cnt)
+ {
+ clk_err("%s:save buf is not Enough\n",__FUNCTION__);
+ return 0;
+ }
+ clk_debug("%s:crubase=%x,gtbase=%x\n",__FUNCTION__,cru_base,gt_base);
+
+ return (u32)(gt_base-cru_base);
+
+}
+
+
+
+
--- /dev/null
+/*
+ * Header providing constants for Rockchip pinctrl bindings.
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
+#define __DT_BINDINGS_ROCKCHIP_PM_H__
+
+/*********************CTRBIT DEFINE*****************************/
+#define RKPM_CTR_PWR_DMNS (0x1<<0)
+#define RKPM_CTR_GTCLKS (0x1<<1)
+#define RKPM_CTR_PLLS (0x1<<2)
+#define RKPM_CTR_VOLTS (0x1<<3)
+#define RKPM_CTR_GPIOS (0x1<<4)
+#define RKPM_CTR_DDR (0x1<<5)
+#define RKPM_CTR_PMIC (0x1<<6)
+ /*
+ *sys_clk 24M div , it is mutex for
+ **RKPM_CTR_SYSCLK_DIV and RKPM_CTR_SYSCLK_32K and RKPM_CTR_SYSCLK_OSC_DIS.
+ **you can select only one
+ */
+#define RKPM_CTR_SYSCLK_DIV (0x1<<7)// system clk is 24M,and div to min
+#define RKPM_CTR_SYSCLK_32K (0x1<<8)// switch sysclk to 32k,need hardwart susport. and div to min
+#define RKPM_CTR_SYSCLK_OSC_DIS (0x1<<9) // switch sysclk to 32k,disable 24M OSC,need hardwart susport. and div to min
+
+ //pm mode Function Selection
+#define RKPM_CTR_NORIDLE_MD (0x1<<16)
+
+ //debug ctrl Selection
+#define RKPM_CTR_RET_DIRT (0x1<<24)
+#define RKPM_CTR_ONLY_WFI (0x1<<25)
+#define RKPM_CTR_SRAM_NO_WFI (0x1<<26)
+#define RKPM_CTR_WAKE_UP_KEY (0x1<<27)
+#define RKPM_CTR_ALL (0x1<<31)
+
+/*********************CTRBIT DEFINE END*****************************/
+
+
+//RKPM_IDX_TO_BITS
+#define RKPM_OR_2BITS(bit1,bit2) ((RKPM_CTR_##bit1)|(RKPM_CTR_##bit2))
+#define RKPM_OR_3BITS(bit1,bit2,bit3) ((RKPM_CTR_##bit1)|RKPM_OR_2BITS(bit2,bit3))
+#define RKPM_OR_4BITS(bit1,bit2,bit3,bit4) ((RKPM_CTR_##bit1)|RKPM_OR_3BITS(bit2,bit3,bit4))
+#define RKPM_OR_5BITS(bit1,bit2,bit3,bit4,bit5) ((RKPM_CTR_##bit1)|RKPM_OR_4BITS(bit2,bit3,bit4,bit5))
+
+/*********************CTRBIT DEFINE END*****************************/
+
+#define RKPM_GPIOBITS_LEVEL_PULL (24)
+#define RKPM_GPIOBITS_MSK_LEVEL_PULL (0xf<<RKPM_GPIOBITS_LEVEL_PULL)
+
+#define RKPM_GPIOBITS_INOUT (20)
+#define RKPM_GPIOBITS_MSK_INOUT (0xf<<RKPM_GPIOBITS_INOUT)
+
+#define RKPM_GPIOBITS_PINS (0)
+#define RKPM_GPIOBITS_MSK_PINS (0xffff<<RKPM_GPIOBITS_PINS)
+
+
+#define RKPM_GPIOS_INPUT (0)
+#define RKPM_GPIOS_OUTPUT (1)
+
+#define RKPM_GPIOS_OUT_H (1)
+#define RKPM_GPIOS_OUT_L (0)
+
+#define RKPM_GPIOS_IN_PULLUP (0)
+#define RKPM_GPIOS_IN_PULLDN (0)
+#define RKPM_GPIOS_IN_PULLNULL (0)
+
+
+#define RKPM_GPIOS_SETTING(pins,in_out,level_pull) (\
+ ((pins)&RKPM_GPIOBITS_MSK_PINS)\
+ |(((in_out)<<RKPM_GPIOBITS_INOUT)&RKPM_GPIOBITS_MSK_INOUT)\
+ |(((level_pull)<<RKPM_GPIOBITS_LEVEL_PULL)&RKPM_GPIOBITS_MSK_LEVEL_PULL)\
+ )
+
+
+#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff