Reduce the amount of state in the lowering code and drop old pattern ISel functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30881 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 51de4e6ba5a2fb08ed573e72f5e088ace13d5667..b3b2461eaf94b0ddd9a95543f0634c35b85d7c8c 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -193,17 +193,33 @@ private:
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+  MachineFunction* MF = BB->getParent();
+  unsigned GP = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+       ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R29) {
+      GP = ii->second;
+      break;
+    }
+  assert(GP && "GOT PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                AlphaLowering.getVRegGP(), 
-                                MVT::i64);
+                                GP, MVT::i64);
 }
 
 /// getRASaveReg - Grab the return address
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
+  MachineFunction* MF = BB->getParent();
+  unsigned RA = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+       ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R26) {
+      RA = ii->second;
+      break;
+    }
+  assert(RA && "RA PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
-                                AlphaLowering.getVRegRA(), 
-                                MVT::i64);
+                                RA, MVT::i64);
 }
 
 /// InstructionSelectBasicBlock - This callback is invoked by

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 5583890727b3ac74334c73ccc3b1204938801ab4..d99df281419bf47c3c7dc5b50cf06dde7df4794e 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -201,17 +201,15 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
                                       int &VarArgsBase,
-                                      int &VarArgsOffset,
-                                      unsigned int &GP,
-                                      unsigned int &RA) {
+                                      int &VarArgsOffset) {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   SSARegMap *RegMap = MF.getSSARegMap();
   std::vector<SDOperand> ArgValues;
   SDOperand Root = Op.getOperand(0);
 
-  GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
-  RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
+  AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
+  AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
 
   unsigned args_int[] = {
     Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
@@ -291,7 +289,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
 }
 
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
+static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 
                                    DAG.getNode(AlphaISD::GlobalRetAddr, 
                                     MVT::i64),
@@ -386,15 +384,6 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
   return std::make_pair(RetVal, Chain);
 }
 
-void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
-{
-  BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
-}
-void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
-{
-  BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
-}
-
 static int getUID()
 {
   static int id = 0;
@@ -408,9 +397,9 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   default: assert(0 && "Wasn't expecting to be able to lower this!");
   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, 
                                                           VarArgsBase,
-                                                          VarArgsOffset,
-                                                          GP, RA);
-  case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
+                                                          VarArgsOffset);
+
+  case ISD::RET: return LowerRET(Op,DAG);
   case ISD::JumpTable: return LowerJumpTable(Op, DAG);
 
   case ISD::SINT_TO_FP: {

diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 3c7ffa1f9d43dfda60c0782d86cb6dbe3ba5dd85..7fd3eef508ee54132ceb3e809c4b5daceb32286c 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -54,8 +54,6 @@ namespace llvm {
   class AlphaTargetLowering : public TargetLowering {
     int VarArgsOffset;  // What is the offset to the first vaarg
     int VarArgsBase;    // What is the base FrameIndex
-    unsigned GP; //GOT vreg
-    unsigned RA; //Return Address
     bool useITOF;
   public:
     AlphaTargetLowering(TargetMachine &TM);
@@ -81,10 +79,6 @@ namespace llvm {
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
 
-    void restoreGP(MachineBasicBlock* BB);
-    void restoreRA(MachineBasicBlock* BB);
-    unsigned getVRegGP() { return GP; }
-    unsigned getVRegRA() { return RA; }
     bool hasITOF() { return useITOF; }
   };
 }