rockchip: clk: rk3399: add clk_testout2 ID
authorElaine Zhang <zhangqing@rock-chips.com>
Wed, 26 Oct 2016 10:04:43 +0000 (18:04 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Thu, 27 Oct 2016 06:22:07 +0000 (14:22 +0800)
Change-Id: If5d94896e8e5ce565738064ab8273dbf7242881e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
include/dt-bindings/clock/rk3399-cru.h

index e5bf167ea38f27ed1ba6cc387f4ed75fe0fd71a5..b5bbc3126fc1502bac05f68c8d8ff97b847eddac 100644 (file)
@@ -1096,7 +1096,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 
        MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
                        RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
-       COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
+       COMPOSITE(SCLK_TESTOUT2, "clk_testout2", mux_clk_testout2_p, 0,
                        RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(13), 15, GFLAGS),
 
index 528c9d93863e6c9a6c13133d3e2393da6fdb5fa2..f04bb81a0605c8e80ee5194cade55674b013538c 100644 (file)
 #define SCLK_USBPHY0_480M_SRC          168
 #define SCLK_USBPHY1_480M_SRC          169
 #define SCLK_DDRCLK                    170
+#define SCLK_TESTOUT2                  171
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181