git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910
91177308-0d34-0410-b5e6-
96231b3b80d8
: T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-20} = op31_20{11-0};
let Inst{15-14} = op15_14{1-0};
+ let Inst{13} = 0b0;
let Inst{12} = op12{0};
+ let Inst{7-0} = 0;
}
class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
bits<4> Rn;
let Inst{19-16} = Rn;
let Inst{20} = mask{4}; // R Bit
- let Inst{13} = 0b0;
let Inst{11-8} = mask{3-0};
}
unsigned pred = fieldFromInstruction32(Insn, 22, 4);
if (pred == 0xE || pred == 0xF) {
- unsigned opc = fieldFromInstruction32(Insn, 4, 2);
+ unsigned opc = fieldFromInstruction32(Insn, 4, 28);
switch (opc) {
default:
return Fail;
- case 0:
+ case 0xf3bf8f4:
Inst.setOpcode(ARM::t2DSB);
break;
- case 1:
+ case 0xf3bf8f5:
Inst.setOpcode(ARM::t2DMB);
break;
- case 2:
+ case 0xf3bf8f6:
Inst.setOpcode(ARM::t2ISB);
return Success;
}