TargetInstrInfo::hasOperandInterlock() is always true, because it is

never overridden by any target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15308 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 8d15c5df95148869bcd762b99208fb7699ed5450..f77ba6f25c0e348567f0f582d3269d6641f8e06b 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -194,18 +194,11 @@ public:
   bool isDummyPhiInstr(MachineOpCode opCode) const {
     return get(opCode).Flags & M_DUMMY_PHI_FLAG;
   }
-  // Check if an instruction can be issued before its operands are ready,
-  // or if a subsequent instruction that uses its result can be issued
-  // before the results are ready.
-  // Default to true since most instructions on many architectures allow this.
-  // 
-  virtual bool hasOperandInterlock(MachineOpCode opCode) const {
-    return true;
-  }  
+
   virtual bool hasResultInterlock(MachineOpCode opCode) const {
     return true;
   }
-  
+
   // 
   // Latencies for individual instructions and instruction pairs
   // 

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 5e66acb06055dfc33ce3e06aa93a41d93fbee6b5..dd2f45dabda1ed784696bd0faf8e098650c79b86 100644 (file)
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
        && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
       return false;
   
-  // for now, don't put an instruction that does not have operand
-  // interlocks in the delay slot of a branch
-  if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
-    return false;
-  
   // Finally, if the instruction precedes the branch, we make sure the
   // instruction can be reordered relative to the branch.  We simply check
   // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
@@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
       const SchedGraphNode* dnode = delayNodeVec[i];
       if ( ! S.isScheduled(dnode)
            && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
-           && instrIsFeasible(S, dnode->getOpcode()))
-      {
-        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
-               && "Instructions without interlocks not yet supported "
-               "when filling branch delay slots");
+           && instrIsFeasible(S, dnode->getOpcode())) {
         S.scheduleInstr(dnode, nextSlot, nextTime);
         break;
       }

diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 5e66acb06055dfc33ce3e06aa93a41d93fbee6b5..dd2f45dabda1ed784696bd0faf8e098650c79b86 100644 (file)
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
        && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
       return false;
   
-  // for now, don't put an instruction that does not have operand
-  // interlocks in the delay slot of a branch
-  if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
-    return false;
-  
   // Finally, if the instruction precedes the branch, we make sure the
   // instruction can be reordered relative to the branch.  We simply check
   // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
@@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
       const SchedGraphNode* dnode = delayNodeVec[i];
       if ( ! S.isScheduled(dnode)
            && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
-           && instrIsFeasible(S, dnode->getOpcode()))
-      {
-        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
-               && "Instructions without interlocks not yet supported "
-               "when filling branch delay slots");
+           && instrIsFeasible(S, dnode->getOpcode())) {
         S.scheduleInstr(dnode, nextSlot, nextTime);
         break;
       }