Required Properties:
- compatible: should be one of the following.
- - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
- - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
- - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
+ - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
+ - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
+ - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
Example: A pin-controller node with pin banks:
pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
Example 1: A pin-controller node with pin groups.
pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
Example 2: A pin-controller node with external wakeup interrupt controller node.
pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-vt8500/
+F: drivers/clocksource/vt8500_timer.c
+F: drivers/gpio/gpio-vt8500.c
+F: drivers/mmc/host/wmt-sdmmc.c
+F: drivers/pwm/pwm-vt8500.c
+F: drivers/rtc/rtc-vt8500.c
+F: drivers/tty/serial/vt8500_serial.c
+F: drivers/usb/host/ehci-vt8500.c
+F: drivers/usb/host/uhci-platform.c
F: drivers/video/vt8500lcdfb.*
F: drivers/video/wm8505fb*
F: drivers/video/wmt_ge_rops.*
-F: drivers/tty/serial/vt8500_serial.c
-F: drivers/rtc/rtc-vt8500.c
-F: drivers/mmc/host/wmt-sdmmc.c
ARM/ZIPIT Z2 SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
F: arch/arm/mach-pxa/z2.c
F: arch/arm/mach-pxa/include/mach/z2.h
+ARM/ZYNQ ARCHITECTURE
+M: Michal Simek <michal.simek@xilinx.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W: http://wiki.xilinx.com
+T: git git://git.xilinx.com/linux-xlnx.git
+S: Supported
+F: arch/arm/mach-zynq/
+
ARM64 PORT (AARCH64 ARCHITECTURE)
M: Catalin Marinas <catalin.marinas@arm.com>
M: Will Deacon <will.deacon@arm.com>
#
choice
prompt "ARM system type"
- default ARCH_MULTIPLATFORM
+ default ARCH_VERSATILE if !MMU
+ default ARCH_MULTIPLATFORM if MMU
config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
bool
select ISA_DMA_API
+config ARCH_NO_VIRT_TO_BUS
+ def_bool y
+ depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
+
# Select ISA DMA interface
config ISA_DMA_API
bool
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x4000>;
interrupts = <5 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
status = "disabled";
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x4000>;
interrupts = <6 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
status = "disabled";
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x4000>;
interrupts = <7 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
status = "disabled";
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x4000>;
interrupts = <8 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
status = "disabled";
};
usart3 {
- pinctrl_uart3: usart3-0 {
+ pinctrl_usart3: usart3-0 {
atmel,pins =
- <2 23 0x2 0x1 /* PC22 periph B with pullup */
+ <2 22 0x2 0x1 /* PC22 periph B with pullup */
2 23 0x2 0x0>; /* PC23 periph B */
};
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x200>;
interrupts = <5 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
status = "disabled";
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x200>;
interrupts = <6 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
status = "disabled";
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x200>;
interrupts = <7 4 5>;
- atmel,use-dma-rx;
- atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
status = "disabled";
reg = <0xd0400 0x20>;
ngpios = <32>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <12>, <13>, <14>, <60>;
};
reg = <0xd0420 0x20>;
ngpios = <32>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <61>;
};
};
pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_2: pinctrl@03860000 {
- compatible = "samsung,pinctrl-exynos4210";
+ compatible = "samsung,exynos4210-pinctrl";
reg = <0x03860000 0x1000>;
};
sd4_bus8: sd4-bus-width8 {
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <3>;
+ samsung,pin-function = <4>;
samsung,pin-pud = <4>;
samsung,pin-drv = <3>;
};
};
pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,pinctrl-exynos4x12";
+ compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,pinctrl-exynos4x12";
+ compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_2: pinctrl@03860000 {
- compatible = "samsung,pinctrl-exynos4x12";
+ compatible = "samsung,exynos4x12-pinctrl";
reg = <0x03860000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <10 0>;
};
pinctrl_3: pinctrl@106E0000 {
- compatible = "samsung,pinctrl-exynos4x12";
+ compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
interrupts = <0 72 0>;
};
};
pinctrl {
- compatible = "samsung,pinctrl-exynos5440";
+ compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
- interrupts = <0 16 0>, <0 17 0>;
+ interrupts = <0 17 0>, <0 16 0>;
};
};
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
- clocks = <&clks 117>, <&clks 117>, <&clks 177>;
+ clocks = <&clks 117>, <&clks 117>, <&clks 190>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
compatible = "arm,sp805", "arm,primecell";
status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
- interrupts = <98>;
+ interrupts = <0 98 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
wdt@2a490000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0 0x2a490000 0 0x1000>;
- interrupts = <98>;
+ interrupts = <0 98 4>;
clocks = <&oscclk6a>, <&oscclk6a>;
clock-names = "wdogclk", "apb_pclk";
};
CONFIG_USB_RCAR_PHY=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
-CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_MARVELL_PHY=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_MV64XXX=y
CONFIG_SERIAL_8250_DW=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=m
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SPI_PL022=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TC3589X=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_AB8500_BM=y
-CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_AB8500_BM is not set
+# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_MFD_STMPE=y
*/
extern void __set_dma_addr(unsigned int chan, void *addr);
#define set_dma_addr(chan, addr) \
- __set_dma_addr(chan, bus_to_virt(addr))
+ __set_dma_addr(chan, (void *)__bus_to_virt(addr))
/* Set the DMA byte count for this channel
*
#define __bus_to_pfn(x) __phys_to_pfn(x)
#endif
+#ifdef CONFIG_VIRT_TO_BUS
static inline __deprecated unsigned long virt_to_bus(void *x)
{
return __virt_to_bus((unsigned long)x);
{
return (void *)__bus_to_virt(x);
}
+#endif
/*
* Conversion between a struct page and a physical address.
void exynos5_restart(char mode, const char *cmd)
{
+ struct device_node *np;
u32 val;
void __iomem *addr;
val = 0x1;
addr = EXYNOS_SWRESET;
} else if (of_machine_is_compatible("samsung,exynos5440")) {
- val = (0x10 << 20) | (0x1 << 16);
- addr = EXYNOS5440_SWRESET;
+ np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
+ addr = of_iomap(np, 0) + 0xcc;
+ val = (0xfff << 20) | (0x1 << 16);
} else {
pr_err("%s: cannot support non-DT\n", __func__);
return;
* interrupt support code here can be completely removed.
*/
static const struct of_device_id exynos_pinctrl_ids[] = {
- { .compatible = "samsung,pinctrl-exynos4210", },
- { .compatible = "samsung,pinctrl-exynos4x12", },
+ { .compatible = "samsung,exynos4210-pinctrl", },
+ { .compatible = "samsung,exynos4x12-pinctrl", },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
/* issue the standby signal into the pm unit. */
cpu_do_idle();
- /* we should never get past here */
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
static void exynos_pm_prepare(void)
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* clear the wakeup state register */
+ __raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
goto early_wakeup;
}
bool "Support Wolfson Microelectronics 1133-EV1 module"
depends on MACH_MX31ADS
depends on MFD_WM8350_I2C
- depends on REGULATOR_WM8350
+ depends on REGULATOR_WM8350 = y
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8352_CONFIG_MODE_0
help
clk_prepare_enable(clk[emi_ahb]);
+ /* Clock source for gpt must be derived from AHB */
+ clk_set_parent(clk[per5_sel], clk[ahb]);
+
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
- clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
- clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
- clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
+ clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
+ clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
+ clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
+ clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
+ clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
+ clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
#include <linux/amba/serial.h>
-#ifdef CONFIG_ARCH_INTEGRATOR_AP
extern struct amba_pl010_data ap_uart_data;
-#else
-/* Not used without Integrator/AP support anyway */
-struct amba_pl010_data ap_uart_data {};
-#endif
void integrator_init_early(void);
int integrator_init(bool is_cp);
void integrator_reserve(void);
* hard-code them. The Integator/CP and forward have proper cell IDs.
* Else we leave them undefined to the bus driver can autoprobe them.
*/
- if (!is_cp) {
+ if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) {
rtc_device.periphid = 0x00041030;
uart0_device.periphid = 0x00041010;
uart1_device.periphid = 0x00041010;
* f1b00000 1b000000 GPIO
*/
-static struct map_desc ap_io_desc[] __initdata = {
+static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
{
.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
static void __init ap_map_io_atag(void)
{
iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
- ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
ap_map_io();
}
platform_device_register(&cfi_flash_device);
+ ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;
* fcb00000 cb000000 CP system control
*/
-static struct map_desc intcp_io_desc[] __initdata = {
+static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
{
.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
(((drvstr) & 0xF) << 17))
int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
-void __init proc_comm_boot_wait(void);
+void proc_comm_boot_wait(void);
#endif
AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
-obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
+obj-y += system-controller.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
-static DEFINE_SPINLOCK(wakeupgen_lock);
+static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = MAX_NR_REG_BANKS;
static unsigned int max_irqs = MAX_IRQS;
{
unsigned long flags;
- spin_lock_irqsave(&wakeupgen_lock, flags);
+ raw_spin_lock_irqsave(&wakeupgen_lock, flags);
_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
- spin_unlock_irqrestore(&wakeupgen_lock, flags);
+ raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
/*
{
unsigned long flags;
- spin_lock_irqsave(&wakeupgen_lock, flags);
+ raw_spin_lock_irqsave(&wakeupgen_lock, flags);
_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
- spin_unlock_irqrestore(&wakeupgen_lock, flags);
+ raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#ifdef CONFIG_HOTPLUG_CPU
{
unsigned long flags;
- spin_lock_irqsave(&wakeupgen_lock, flags);
+ raw_spin_lock_irqsave(&wakeupgen_lock, flags);
if (set) {
_wakeupgen_save_masks(cpu);
_wakeupgen_set_all(cpu, WKG_MASK_ALL);
_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
_wakeupgen_restore_masks(cpu);
}
- spin_unlock_irqrestore(&wakeupgen_lock, flags);
+ raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#endif
int r = 0;
if (of_have_populated_dt()) {
- np = omap_get_timer_dt(omap_timer_match, NULL);
+ np = omap_get_timer_dt(omap_timer_match, property);
if (!np)
return -ENODEV;
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/gpio.h>
+#include <linux/string.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
struct twl4030_platform_data *pmic_data)
{
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
- strncpy(pmic_i2c_board_info.type, pmic_type,
+ strlcpy(pmic_i2c_board_info.type, pmic_type,
sizeof(pmic_i2c_board_info.type));
pmic_i2c_board_info.irq = pmic_irq;
pmic_i2c_board_info.platform_data = pmic_data;
#define GPIO_NR_TREO_LCD_POWER 25
/* Treo680 specific GPIOs */
-#ifdef CONFIG_MACH_TREO680
#define GPIO_NR_TREO680_SD_READONLY 33
#define GPIO_NR_TREO680_SD_POWER 42
#define GPIO_NR_TREO680_VIBRATE_EN 44
#define GPIO_NR_TREO680_KEYB_BL 24
#define GPIO_NR_TREO680_BT_EN 43
-#endif /* CONFIG_MACH_TREO680 */
+#define GPIO_NR_TREO680_LCD_POWER 77
+#define GPIO_NR_TREO680_LCD_EN 86
+#define GPIO_NR_TREO680_LCD_EN_N 25
/* Centro685 specific GPIOs */
#define GPIO_NR_CENTRO_SD_POWER 21
#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */
#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */
#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */
+#define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */
/*
* More handy macros for PCMCIA
GPIO96_KP_MKOUT_6,
GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
/* Quick Capture Interface */
GPIO84_CIF_FV,
GPIO85_CIF_LV,
/* MATRIX KEYPAD - different wake up source */
GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
GPIO99_KP_MKIN_5,
+
+ /* LCD... L_BIAS alt fn not configured on Treo680; is GPIO instead */
+ GPIOxx_LCD_16BPP,
+ GPIO74_LCD_FCLK,
+ GPIO75_LCD_LCLK,
+ GPIO76_LCD_PCLK,
};
#endif /* CONFIG_MACH_TREO680 */
/* MATRIX KEYPAD - different wake up source */
GPIO100_KP_MKIN_0,
GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+
+ /* LCD */
+ GPIOxx_LCD_TFT_16BPP,
};
#endif /* CONFIG_MACH_CENTRO */
/******************************************************************************
* Vibra and LEDs
******************************************************************************/
-#ifdef CONFIG_MACH_TREO680
static struct gpio_led treo680_gpio_leds[] = {
{
.name = "treo680:vibra:vibra",
static struct platform_device palmtreo_leds = {
.name = "leds-gpio",
.id = -1,
- .dev = {
- .platform_data = &treo680_gpio_led_info,
- }
};
static void __init palmtreo_leds_init(void)
{
if (machine_is_centro())
palmtreo_leds.dev.platform_data = ¢ro_gpio_led_info;
+ else if (machine_is_treo680())
+ palmtreo_leds.dev.platform_data = &treo680_gpio_led_info;
platform_device_register(&palmtreo_leds);
}
-#else
-static inline void palmtreo_leds_init(void) {}
-#endif
/******************************************************************************
* Machine init
}
#ifdef CONFIG_MACH_TREO680
+void __init treo680_gpio_init(void)
+{
+ unsigned int gpio;
+
+ /* drive all three lcd gpios high initially */
+ const unsigned long lcd_flags = GPIOF_INIT_HIGH | GPIOF_DIR_OUT;
+
+ /*
+ * LCD GPIO initialization...
+ */
+
+ /*
+ * This is likely the power to the lcd. Toggling it low/high appears to
+ * turn the lcd off/on. Can be toggled after lcd is initialized without
+ * any apparent adverse effects to the lcd operation. Note that this
+ * gpio line is used by the lcd controller as the L_BIAS signal, but
+ * treo680 configures it as gpio.
+ */
+ gpio = GPIO_NR_TREO680_LCD_POWER;
+ if (gpio_request_one(gpio, lcd_flags, "LCD power") < 0)
+ goto fail;
+
+ /*
+ * These two are called "enables", for lack of a better understanding.
+ * If either of these are toggled after the lcd is initialized, the
+ * image becomes degraded. N.B. The IPL shipped with the treo
+ * configures GPIO_NR_TREO680_LCD_EN_N as output and drives it high. If
+ * the IPL is ever reprogrammed, this initialization may be need to be
+ * revisited.
+ */
+ gpio = GPIO_NR_TREO680_LCD_EN;
+ if (gpio_request_one(gpio, lcd_flags, "LCD enable") < 0)
+ goto fail;
+ gpio = GPIO_NR_TREO680_LCD_EN_N;
+ if (gpio_request_one(gpio, lcd_flags, "LCD enable_n") < 0)
+ goto fail;
+
+ /* driving this low turns LCD on */
+ gpio_set_value(GPIO_NR_TREO680_LCD_EN_N, 0);
+
+ return;
+ fail:
+ pr_err("gpio %d initialization failed\n", gpio);
+ gpio_free(GPIO_NR_TREO680_LCD_POWER);
+ gpio_free(GPIO_NR_TREO680_LCD_EN);
+ gpio_free(GPIO_NR_TREO680_LCD_EN_N);
+}
+
static void __init treo680_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
palmphone_common_init();
+ treo680_gpio_init();
palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
GPIO_NR_TREO680_SD_POWER, 0);
}
__raw_writel(csadrcfg[1], CSADRCFG1);
__raw_writel(csadrcfg[2], CSADRCFG2);
__raw_writel(csadrcfg[3], CSADRCFG3);
+ /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
+ __raw_writel(0x2, CSMSADRCFG);
}
static struct syscore_ops smemc_syscore_ops = {
static int __init smemc_init(void)
{
- if (cpu_is_pxa3xx())
+ if (cpu_is_pxa3xx()) {
+ /*
+ * The only documentation we have on the
+ * Chip Select Configuration Register (CSMSADRCFG) is that
+ * it must be programmed to 0x2.
+ * Moreover, in the bit definitions, the second bit
+ * (CSMSADRCFG[1]) is called "SETALWAYS".
+ * Other bits are reserved in this register.
+ */
+ __raw_writel(0x2, CSMSADRCFG);
+
register_syscore_ops(&smemc_syscore_ops);
+ }
return 0;
}
#endif
/******************************************************************************
- * Framebuffer
+ * NAND Flash
******************************************************************************/
#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
static struct mtd_partition spitz_nand_partitions[] = {
#endif
/******************************************************************************
- * GPIO expander
+ * I2C devices
******************************************************************************/
#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
static struct pca953x_platform_data akita_pca953x_pdata = {
config ARCH_SMDK2410
bool "SMDK2410/A9M2410"
select S3C24XX_SMDK
+ select S3C_DEV_USB_HOST
help
Say Y here if you are using the SMDK2410 or the derived module A9M2410
<http://www.fsforth.de>
config S3C2412_PM
bool
+ select S3C2412_PM_SLEEP
help
Internal config node to apply S3C2412 power management
[3] = &clk_mpllref,
};
-struct clksrc_clk clk_msysclk = {
+static struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
static void s3c24xx_default_idle(void)
{
- unsigned long tmp;
+ unsigned long tmp = 0;
int i;
/* idle the system by using the idle mode which will wait for an
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
- ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+ ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
1004:
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
moveq \rd, \rd, lsr #SHIFT_2440TXF
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
.macro fifo_full_s3c2410 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
- ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+ ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
10000:
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
.macro fifo_level_s3c2410 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
@@ try the interrupt offset register, since it is there
- ldr \irqstat, [ \base, #INTPND ]
+ ldr \irqstat, [\base, #INTPND ]
teq \irqstat, #0
beq 1002f
- ldr \irqnr, [ \base, #INTOFFSET ]
+ ldr \irqnr, [\base, #INTOFFSET ]
mov \tmp, #1
tst \irqstat, \tmp, lsl \irqnr
bne 1001f
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>
+#include <linux/platform_device.h>
#include <linux/i2c/tps65010.h>
h1940_pm_return:
mov r0, #S3C2410_PA_GPIO
- ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
+ ldr pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
s3c2412_sleep_enter();
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
static void s3c2412_pm_prepare(void)
s3c2412_sleep_enter();
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
static void s3c2416_pm_prepare(void)
ldr r4, =S3C2410_REFRESH
ldr r5, =S3C24XX_MISCCR
ldr r6, =S3C2410_CLKCON
- ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
- ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
- ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
+ ldr r7, [r4] @ get REFRESH (and ensure in TLB)
+ ldr r8, [r5] @ get MISCCR (and ensure in TLB)
+ ldr r9, [r6] @ get CLKCON (and ensure in TLB)
orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
@@ align next bit of code to cache line
.align 5
s3c2410_do_sleep:
- streq r7, [ r4 ] @ SDRAM sleep command
- streq r8, [ r5 ] @ SDRAM power-down config
- streq r9, [ r6 ] @ CPU sleep
+ streq r7, [r4] @ SDRAM sleep command
+ streq r8, [r5] @ SDRAM power-down config
+ streq r9, [r6] @ CPU sleep
1: beq 1b
mov pc, r14
* retry, as simply returning causes the system to lock.
*/
- ldrne r9, [ r1 ]
- strne r9, [ r1 ]
- ldrne r9, [ r2 ]
- strne r9, [ r2 ]
- ldrne r9, [ r3 ]
- strne r9, [ r3 ]
+ ldrne r9, [r1]
+ strne r9, [r1]
+ ldrne r9, [r2]
+ strne r9, [r2]
+ ldrne r9, [r3]
+ strne r9, [r3]
bne s3c2412_sleep_enter1
mov pc, r14
/* we should never get past here */
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
/* mapping of interrupts to parts of the wakeup mask */
"mcr p15, 0, %0, c7, c10, 4\n\t"
"mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
- /* we should never get past here */
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
/* mapping of interrupts to parts of the wakeup mask */
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
+ fifo_mask = S5PV210_UFSTAT_TXMASK;
+ fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
"mcr p15, 0, %0, c7, c10, 4\n\t"
"wfi" : : "r" (tmp));
- /* we should never get past here */
- panic("sleep resumed to originator?");
+ pr_info("Failed to suspend the system\n");
+ return 1; /* Aborting suspend */
}
static void s5pv210_pm_prepare(void)
#include "generic.h"
-
-#warning "include/asm/arch-sa1100/ide.h needs fixing for lart"
-
static struct mcp_plat_data lart_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
* Init clocks here so that they are available for system timer
* initialization.
*/
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_u9540())
db8500_prcmu_early_init();
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_u9540())
u8500_clk_init();
- else if (cpu_is_u9540())
- u9540_clk_init();
else if (cpu_is_u8540())
u8540_clk_init();
}
goto wfi;
/* decouple the gic from the A9 cores */
- if (prcmu_gic_decouple())
+ if (prcmu_gic_decouple()) {
+ spin_unlock(&master_lock);
goto out;
+ }
/* If an error occur, we will have to recouple the gic
* manually */
Include support for the ARM(R) Versatile/PB platform,
using the device tree for discovery
+config MACH_VERSATILE_AUTO
+ def_bool y
+ depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB
+ select MACH_VERSATILE_DT
+
endmenu
writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
}
-static struct map_desc versatile_io_desc[] __initdata = {
+static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
{
.virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
.pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
mov \base, #AIC_BA
- ldr \irqnr, [ \base, #AIC_IPER]
- ldr \irqnr, [ \base, #AIC_ISNR]
+ ldr \irqnr, [\base, #AIC_IPER]
+ ldr \irqnr, [\base, #AIC_ISNR]
cmp \irqnr, #0
.endm
errata = p->errata;
if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
- && (omap_dma_reserve_channels <= dma_lch_count))
+ && (omap_dma_reserve_channels < d->lch_count))
d->lch_count = omap_dma_reserve_channels;
dma_lch_count = d->lch_count;
"number (%u)\n", num);
continue;
}
- if (variant_mask & !(*mpp_list & variant_mask)) {
+ if (variant_mask && !(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"orion_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
/* The S5PV210/S5PC110 implementations are as belows. */
.macro fifo_level_s5pv210 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S5PV210_UFSTAT_TXMASK
.endm
.macro fifo_full_s5pv210 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S5PV210_UFSTAT_TXFULL
.endm
* most widely re-used */
.macro fifo_level_s3c2440 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
#endif
.macro fifo_full_s3c2440 rd, rx
- ldr \rd, [ \rx, # S3C2410_UFSTAT ]
+ ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2440_UFSTAT_TXFULL
.endm
#endif
.macro senduart,rd,rx
- strb \rd, [\rx, # S3C2410_UTXH ]
+ strb \rd, [\rx, # S3C2410_UTXH]
.endm
.macro busyuart, rd, rx
- ldr \rd, [ \rx, # S3C2410_UFCON ]
+ ldr \rd, [\rx, # S3C2410_UFCON]
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
1001:
@ busy waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
+ ldr \rd, [\rx, # S3C2410_UTRSTAT]
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
.endm
.macro waituart,rd,rx
- ldr \rd, [ \rx, # S3C2410_UFCON ]
+ ldr \rd, [\rx, # S3C2410_UFCON]
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
b 1002f
1001:
@ idle waiting for non fifo
- ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
+ ldr \rd, [\rx, # S3C2410_UTRSTAT]
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
s5p_device_fimc3.name = name;
break;
#endif
+ default:
+ break;
}
}
s3c_device_hsmmc3.name = name;
break;
#endif
+ default:
+ break;
}
}
char buff[256];
va_start(va, fmt);
- vsprintf(buff, fmt, va);
+ vsnprintf(buff, sizeof(buff), fmt, va);
va_end(va);
printascii(buff);
static int s3c_pm_enter(suspend_state_t state)
{
+ int ret;
/* ensure the debug is initialised (if enabled) */
s3c_pm_debug_init();
* we resume as it saves its own register state and restores it
* during the resume. */
- cpu_suspend(0, pm_cpu_sleep);
+ ret = cpu_suspend(0, pm_cpu_sleep);
+ if (ret)
+ return ret;
/* restore the system state */
config ARCH_SPEAR13XX
bool "ST SPEAr13xx with Device Tree"
+ select ARCH_HAVE_CPUFREQ
select ARM_GIC
select CPU_V7
select GPIO_SPEAR_SPICS
*/
struct device_node *pctrl_np;
static const struct of_device_id exynos_pinctrl_ids[] = {
- { .compatible = "samsung,pinctrl-exynos4210", },
- { .compatible = "samsung,pinctrl-exynos4x12", },
- { .compatible = "samsung,pinctrl-exynos5440", },
+ { .compatible = "samsung,exynos4210-pinctrl", },
+ { .compatible = "samsung,exynos4x12-pinctrl", },
+ { .compatible = "samsung,exynos5440-pinctrl", },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np && of_device_is_available(pctrl_np))
}
-void __init vexpress_sysreg_setup(struct device_node *node)
+void vexpress_sysreg_setup(struct device_node *node)
{
if (WARN_ON(!vexpress_sysreg_base))
return;
}
static const struct of_device_id samsung_pinctrl_dt_match[] = {
- { .compatible = "samsung,pinctrl-exynos4210",
+ { .compatible = "samsung,exynos4210-pinctrl",
.data = (void *)exynos4210_pin_ctrl },
- { .compatible = "samsung,pinctrl-exynos4x12",
+ { .compatible = "samsung,exynos4x12-pinctrl",
.data = (void *)exynos4x12_pin_ctrl },
{},
};
#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
+struct platform_device;
+
/**
* struct s3c2410_platform_i2c - Platform data for s3c I2C.
* @bus_num: The bus number to use (if possible).
_r(&sort_needed_sym->st_value) -
_r(&sort_needed_sec->sh_addr);
-#if 1
+#if 0
printf("sort done marker at %lx\n",
(unsigned long)((char *)sort_done_location - (char *)ehdr));
#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff