lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
rockchip,grf = <&grf>;
- reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
+ reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&clk_gates22 10>, <&clk_gates17 3>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
pinctrl_select_state(lvds->pins->p,
lvds->pins->default_state);
#endif
+ lvds_dsi_writel(lvds, 0x0, 0x4);/*set clock lane enable*/
/* enable lvds mode */
val |= v_RK3368_LVDSMODE_EN(0) | v_RK3368_MIPIPHY_TTL_EN(1) |
v_RK3368_MIPIPHY_LANE0_EN(1) |
return 0;
}
+static inline int lvds_dsi_writel(struct rk_lvds_device *lvds,
+ u32 offset, u32 val)
+{
+ writel_relaxed(val, lvds->ctrl_reg + offset);
+ dsb(sy);
+
+ return 0;
+}
+
static inline u32 lvds_phy_lockon(struct rk_lvds_device *lvds)
{
u32 val = 0;
- val = readl_relaxed(lvds->ctrl_reg);
+ val = readl_relaxed(lvds->ctrl_reg + 0x10);
return (val & 0x01);
}