#define BIT_VCODEC_SEL_RK312X (1<<15)\r
static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)\r
{\r
- if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128()) {\r
- int bits = soc_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
- void __iomem *addr = soc_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
+ if (cpu_is_rk3036() || cpu_is_rk312x()) {\r
+ int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
+ void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
if (reserved_mode)\r
*reserved_mode = readl_relaxed(addr);\r
if (id == VCODEC_DEVICE_ID_HEVC)\r
\r
static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)\r
{\r
- if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128()) {\r
- int bits = soc_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
- void __iomem *addr = soc_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
+ if (cpu_is_rk3036() || cpu_is_rk312x()) {\r
+ int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
+ void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
writel_relaxed(reserved_mode | (bits << 16), addr);\r
}\r
}\r
\r
static void vcodec_enter_mode(enum vcodec_device_id id)\r
{\r
- if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128())\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
mutex_lock(&g_mode_mutex);\r
vcodec_enter_mode_nolock(id, NULL);\r
}\r
\r
static void vcodec_exit_mode(void)\r
{\r
- if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128())\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
mutex_unlock(&g_mode_mutex);\r
}\r
\r
break;\r
}\r
\r
- if (!soc_is_rk3036() && !soc_is_rk3126() && !soc_is_rk3128()) {\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
if (IS_ERR(pservice->clk_cabac)) {\r
dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
pservice->clk_cabac = NULL;\r
}\r
\r
- if (!soc_is_rk3036() && !soc_is_rk3126() && !soc_is_rk3128()) {\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
if (IS_ERR(pservice->pd_video)) {\r
dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
pservice->pd_video = NULL;\r
}\r
} else {\r
- if (!soc_is_rk3036() && !soc_is_rk3126() && !soc_is_rk3128()) {\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
if (IS_ERR(pservice->pd_video)) {\r
dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
}\r
}\r
\r
- if (soc_is_rk3126() || soc_is_rk3128()) {\r
+ if (cpu_is_rk312x()) {\r
pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
if (IS_ERR(pservice->pd_video)) {\r
dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
\r
return 0;\r
}\r
-#if 1\r
+\r
static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
{\r
int ret = -EINVAL, i = 0;\r
iounmap((void *)tmp);\r
return ret;\r
}\r
-#endif\r
\r
static int vpu_service_open(struct inode *inode, struct file *filp)\r
{\r
struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
char *prop = (char*)dev_name(dev);\r
#if defined(CONFIG_VCODEC_MMU)\r
+ u32 iommu_en = 0;\r
char mmu_dev_dts_name[40];\r
+ of_property_read_u32(np, "iommu_enabled", &iommu_en);\r
#endif\r
\r
pr_info("probe device %s\n", dev_name(dev));\r
pservice->reg_pproc = NULL;\r
atomic_set(&pservice->total_running, 0);\r
pservice->enabled = false;\r
-#if defined(CONFIG_VCODEC_MMU) \r
+#if defined(CONFIG_VCODEC_MMU)\r
pservice->mmu_dev = NULL;\r
#endif\r
pservice->dev = dev;\r
\r
{\r
u32 offset = res->start;\r
- if (soc_is_rk3036()) {\r
+ if (cpu_is_rk3036()) {\r
if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)\r
offset += 0x400;\r
}\r
\r
pservice->reg_size = pservice->dec_dev.iosize;\r
\r
- if (pservice->hw_info->hw_id != HEVC_ID && !soc_is_rk3036()) {\r
+ if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {\r
pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;\r
\r
#endif\r
\r
#if defined(CONFIG_VCODEC_MMU)\r
- pservice->ion_client = rockchip_ion_client_create("vpu");\r
- if (IS_ERR(pservice->ion_client)) {\r
- dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
- return PTR_ERR(pservice->ion_client);\r
- } else {\r
- dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
- }\r
+ if (iommu_en) {\r
+ pservice->ion_client = rockchip_ion_client_create("vpu");\r
+ if (IS_ERR(pservice->ion_client)) {\r
+ dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
+ return PTR_ERR(pservice->ion_client);\r
+ } else {\r
+ dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
+ }\r
\r
- if (pservice->hw_info->hw_id == HEVC_ID)\r
- sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
- else\r
- sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
- pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
+ if (pservice->hw_info->hw_id == HEVC_ID)\r
+ sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
+ else\r
+ sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
\r
- if (pservice->mmu_dev) {\r
- platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
- iovmm_activate(pservice->dev);\r
+ pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
+\r
+ if (pservice->mmu_dev) {\r
+ platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
+ iovmm_activate(pservice->dev);\r
+ }\r
}\r
#endif\r
\r
\r
if (soc_is_rk3190() || soc_is_rk3288())\r
dec->maxDecPicWidth = 4096;\r
- else if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128())\r
+ else if (cpu_is_rk3036() || cpu_is_rk312x())\r
dec->maxDecPicWidth = 1920;\r
else\r
dec->maxDecPicWidth = configReg & 0x07FFU;\r
dec->refBufSupport |= 8; /* enable HW support for offset */\r
\r
/// invalidate fuse register value in rk319x vpu and following.\r
- if (!soc_is_rk3190() && !soc_is_rk3288() && !soc_is_rk3036() && !soc_is_rk3126() && !soc_is_rk3128()) {\r
+ if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {\r
VPUHwFuseStatus_t hwFuseSts;\r
/* Decoder fuse configuration */\r
u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
}\r
}\r
\r
- if (!soc_is_rk3036()) {\r
+ if (!cpu_is_rk3036()) {\r
configReg = pservice->enc_dev.hwregs[63];\r
enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
enc->h264Enabled = (configReg >> 27) & 1;\r
\r
pservice->bug_dec_addr = cpu_is_rk30xx();\r
} else {\r
- if (soc_is_rk3036() || soc_is_rk3126() || soc_is_rk3128())\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
dec->maxDecPicWidth = 1920;\r
else\r
dec->maxDecPicWidth = 4096;\r
#if defined(CONFIG_IEP_IOMMU)\r
struct iep_mem_region *mem_region = NULL, *n;\r
// release memory region attach to this registers table.\r
- list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {\r
- ion_unmap_iommu(iep_service.iommu_dev, iep_service.ion_client, mem_region->hdl);\r
- ion_free(iep_service.ion_client, mem_region->hdl);\r
- list_del_init(&mem_region->reg_lnk);\r
- kfree(mem_region);\r
+ if (iep_service.iommu_dev) {\r
+ list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {\r
+ ion_unmap_iommu(iep_service.iommu_dev, iep_service.ion_client, mem_region->hdl);\r
+ ion_free(iep_service.ion_client, mem_region->hdl);\r
+ list_del_init(&mem_region->reg_lnk);\r
+ kfree(mem_region);\r
+ }\r
}\r
#endif \r
list_del_init(®->session_link);\r
int ret = 0;\r
struct resource *res = NULL;\r
#if defined(CONFIG_IEP_IOMMU)\r
+ u32 iommu_en = 0;\r
struct device *mmu_dev = NULL;\r
+ struct device_node *np = pdev->dev.of_node;\r
+ of_property_read_u32(np, "iommu_enabled", &iommu_en);\r
#endif\r
\r
data = (struct iep_drvdata*)devm_kzalloc(&pdev->dev, sizeof(struct iep_drvdata), GFP_KERNEL);\r
\r
#if defined(CONFIG_IEP_IOMMU)\r
iep_service.iommu_dev = NULL;\r
- iep_power_on();\r
- iep_service.ion_client = rockchip_ion_client_create("iep");\r
- if (IS_ERR(iep_service.ion_client)) {\r
- IEP_ERR("failed to create ion client for vcodec");\r
- return PTR_ERR(iep_service.ion_client);\r
- } else {\r
- IEP_INFO("iep ion client create success!\n");\r
- }\r
- \r
- mmu_dev = rockchip_get_sysmmu_device_by_compatible("iommu,iep_mmu");\r
- \r
- if (mmu_dev) {\r
- platform_set_sysmmu(mmu_dev, &pdev->dev);\r
- iovmm_activate(&pdev->dev);\r
+ if (iommu_en) {\r
+ iep_power_on();\r
+ iep_service.ion_client = rockchip_ion_client_create("iep");\r
+ if (IS_ERR(iep_service.ion_client)) {\r
+ IEP_ERR("failed to create ion client for vcodec");\r
+ return PTR_ERR(iep_service.ion_client);\r
+ } else {\r
+ IEP_INFO("iep ion client create success!\n");\r
+ }\r
+\r
+ mmu_dev = rockchip_get_sysmmu_device_by_compatible("iommu,iep_mmu");\r
+ \r
+ if (mmu_dev) {\r
+ platform_set_sysmmu(mmu_dev, &pdev->dev);\r
+ iovmm_activate(&pdev->dev);\r
+ }\r
+\r
+ iep_service.iommu_dev = &pdev->dev;\r
+ iep_power_off();\r
}\r
- \r
- iep_service.iommu_dev = &pdev->dev;\r
- iep_power_off();\r
#endif\r
\r
IEP_INFO("IEP Driver loaded succesfully\n");\r