ARM VFP optional data type on VMOV GPR<-->SPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index e232ed3b5827883213bcfe5b34b2f088d2d5bb23..e6bf1331c2c223a88431fb7a909a1f3d708946d9 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -1240,10 +1240,18 @@ def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
 def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
                     (VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
 
-// VMOV can accept optional .f32/.f64 suffix.
-def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",
+// VMOV can accept optional 32-bit or less data type suffix suffix.
+def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
                     (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
-def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt",
+def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
+                    (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
+                    (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
+                    (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
+                    (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
                     (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
 
 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",

diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s
index 58abe8894be8357bf0a51f0c918e90955c939535..d5d5349a1531c5febd562f942c051e0260307d50 100644 (file)
--- a/test/MC/ARM/simple-fp-encoding.s
+++ b/test/MC/ARM/simple-fp-encoding.s
@@ -271,3 +271,31 @@
 
 @ CHECK: vmovne        s25, s26, r2, r5
         vmovne s25, s26, r2, r5        @ encoding: [0x39,0x2a,0x45,0x1c]
+
+@ VMOV w/ optional data type suffix.
+       vmov.32 s1, r8
+        vmov.s16 s2, r4
+        vmov.16 s3, r6
+        vmov.u32 s4, r1
+        vmov.p8 s5, r2
+        vmov.8 s6, r3
+
+        vmov.32 r1, s8
+        vmov.s16 r2, s4
+        vmov.16 r3, s6
+        vmov.u32 r4, s1
+        vmov.p8 r5, s2
+        vmov.8 r6, s3
+
+@ CHECK: vmov  s1, r8                  @ encoding: [0x90,0x8a,0x00,0xee]
+@ CHECK: vmov  s2, r4                  @ encoding: [0x10,0x4a,0x01,0xee]
+@ CHECK: vmov  s3, r6                  @ encoding: [0x90,0x6a,0x01,0xee]
+@ CHECK: vmov  s4, r1                  @ encoding: [0x10,0x1a,0x02,0xee]
+@ CHECK: vmov  s5, r2                  @ encoding: [0x90,0x2a,0x02,0xee]
+@ CHECK: vmov  s6, r3                  @ encoding: [0x10,0x3a,0x03,0xee]
+@ CHECK: vmov  r1, s8                  @ encoding: [0x10,0x1a,0x14,0xee]
+@ CHECK: vmov  r2, s4                  @ encoding: [0x10,0x2a,0x12,0xee]
+@ CHECK: vmov  r3, s6                  @ encoding: [0x10,0x3a,0x13,0xee]
+@ CHECK: vmov  r4, s1                  @ encoding: [0x90,0x4a,0x10,0xee]
+@ CHECK: vmov  r5, s2                  @ encoding: [0x10,0x5a,0x11,0xee]
+@ CHECK: vmov  r6, s3                  @ encoding: [0x90,0x6a,0x11,0xee]