Add encoding for ARM "trap" instruction.
authorBill Wendling <isanbard@gmail.com>
Sun, 21 Nov 2010 11:05:29 +0000 (11:05 +0000)
committerBill Wendling <isanbard@gmail.com>
Sun, 21 Nov 2010 11:05:29 +0000 (11:05 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.td
test/MC/ARM/arm_instructions.s
test/MC/ARM/simple-encoding.ll
test/MC/ARM/thumb.s

index 4a142c631c746c6c24ea84fa35dcf1694f51a91f..4e4fb2e990d9b3a3b3539607f76c44b3bd51c5f2 100644 (file)
@@ -1130,10 +1130,7 @@ let isBarrier = 1, isTerminator = 1 in
 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
                "trap", [(trap)]>,
            Requires<[IsARM]> {
-  let Inst{27-25} = 0b011;
-  let Inst{24-20} = 0b11111;
-  let Inst{7-5} = 0b111;
-  let Inst{4} = 0b1;
+  let Inst = 0xe7ffdefe;
 }
 
 // Address computation and loads and stores in PIC mode.
index 5bce41d52a2c3003d35b38099566d3e98e7af2a5..a1041fb724b52aa0a6ca327ebb7f3986fc0416a9 100644 (file)
@@ -8,6 +8,10 @@
 @ CHECK: encoding: [0x00,0xf0,0x20,0x03]
         nopeq
 
+@ CHECK: trap
+@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
+        trap
+
 @ CHECK: bx    lr
 @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
         bx lr
index f279bdaa6347c44c3a9c29df4adb44b6e55b4bb0..0877e8e30c6f199d2099774eddd2000a302a34a5 100644 (file)
@@ -12,7 +12,7 @@ declare i32 @llvm.ctlz.i32(i32)
 
 define i32 @foo(i32 %a, i32 %b) {
 ; CHECK: foo
-; CHECK: trap                         @ encoding: [0xf0,0x00,0xf0,0x07]
+; CHECK: trap                         @ encoding: [0xfe,0xde,0xff,0xe7]
 ; CHECK: bx lr                        @ encoding: [0x1e,0xff,0x2f,0xe1]
 
   tail call void @llvm.trap()
index 90e66f8707c736690afe3dc10df164164520ec0c..4b9b5a3a94ba264ec7dfa887e892985de3ee63d4 100644 (file)
@@ -6,3 +6,6 @@
 
 @ CHECK: pop    {r1, r2, r4}         @ encoding: [0x16,0xbc]
         pop     {r1, r2, r4}
+
+@ CHECK: trap                        @ encoding: [0xfe,0xde]
+        trap