def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
"trap", [(trap)]>,
Requires<[IsARM]> {
- let Inst{27-25} = 0b011;
- let Inst{24-20} = 0b11111;
- let Inst{7-5} = 0b111;
- let Inst{4} = 0b1;
+ let Inst = 0xe7ffdefe;
}
// Address computation and loads and stores in PIC mode.
@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
nopeq
+@ CHECK: trap
+@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
+ trap
+
@ CHECK: bx lr
@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
bx lr
define i32 @foo(i32 %a, i32 %b) {
; CHECK: foo
-; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
+; CHECK: trap @ encoding: [0xfe,0xde,0xff,0xe7]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
tail call void @llvm.trap()
@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc]
pop {r1, r2, r4}
+
+@ CHECK: trap @ encoding: [0xfe,0xde]
+ trap