ARM .req register name aliases are case insensitive, just like regnames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 94631890accb2cf92fda0f032d6ecda901b009ef..667418cf120a18f29f7beb2e3e2eb2d2c37e48ca 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2325,9 +2325,10 @@ int ARMAsmParser::tryParseRegister() {
       .Default(0);
   }
   if (!RegNum) {
-    // Check for aliases registered via .req.
-    StringMap<unsigned>::const_iterator Entry =
-      RegisterReqs.find(Tok.getIdentifier());
+    // Check for aliases registered via .req. Canonicalize to lower case.
+    // That's more consistent since register names are case insensitive, and
+    // it's how the original entry was passed in from MC/MCParser/AsmParser.
+    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
     // If no match, return failure.
     if (Entry == RegisterReqs.end())
       return -1;