Be less conservative about forming IT blocks.

In http://reviews.llvm.org/rL215382, IT forming was made more conservative under
the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M.

But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for
v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an
IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block
as long as the flags register is dead afterwards.

This gives significant performance improvements in a variety of MPEG based workloads.

Differential revision: http://reviews.llvm.org/D11680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243869 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9f43e732bd73ba2ace53226ef7895331ad86a110..3eb21ad70775dbbdeff4508a2449ffc9422d322a 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -518,7 +518,7 @@ bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
 
 static bool isCPSRDefined(const MachineInstr *MI) {
   for (const auto &MO : MI->operands())
-    if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
+    if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
       return true;
   return false;
 }

diff --git a/test/CodeGen/ARM/thumb2-it-block.ll b/test/CodeGen/ARM/thumb2-it-block.ll
index 2675a733da97e9a8af80160023ad284f9a6f4c2e..aaefc0a1486392582652b1c410a1a4fe8dbf063f 100644 (file)
--- a/test/CodeGen/ARM/thumb2-it-block.ll
+++ b/test/CodeGen/ARM/thumb2-it-block.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck -check-prefix CHECK-V7 %s
-; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s -check-prefix CHECK-V8
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s
 ; PR11107
 
 define i32 @test(i32 %a, i32 %b) {
@@ -14,17 +14,13 @@ entry:
  ret i32 %add
 }
 
-; CHECK-V7:        cmp
-; CHECK-V7-NEXT:   it    mi
-; CHECK-V7-NEXT:   rsbmi
-; CHECK-V7-NEXT:   cmp
-; CHECK-V7-NEXT:   it    mi
-; CHECK-V7-NEXT:   rsbmi
+; CHECK:        cmp
+; CHECK-NEXT:   it    mi
+; We shouldn't need to check for the extra 's' here; tRSB should be printed as
+; "rsb" inside an IT block, not "rsbs".
+; CHECK-NEXT:   rsb{{s?}}mi
+; CHECK-NEXT:   cmp
+; CHECK-NEXT:   it    mi
+; CHECK-NEXT:   rsb{{s?}}mi
 
-; CHECK-V8:        cmp
-; CHECK-V8-NEXT:   bpl
-; CHECK-V8:        rsbs
-; CHECK-V8:        cmp
-; CHECK-V8-NEXT:   bpl
-; CHECK-V8:        rsbs