Fix ldmxcsr JIT encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31343 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 7361c70cdfeee3490b6c3a02f7bac91cb1c6310d..f7b8d6142845709a550226b345239281caca7ea9 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1653,12 +1653,10 @@ def MFENCE : I<0xAE, MRM6m, (ops),
                "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
 
 // MXCSR register
-def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
-                "ldmxcsr $src",
-                [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
-def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
-                "stmxcsr $dst",
-                [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
+def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
+                  "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
+def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
+                  "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
 
 // Thread synchronization
 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",