Pass in a value type to getRegForInlineAsmConstraint, allowing targets to

select different sets of registers depending on the type requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26304 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 49b35d3bd3aabb53192d68daf8be11c001fde0dd..0e51930442e6a9072f0012aa9abca342bf261543 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -496,7 +496,8 @@ public:
   /// satisfy the constraint.  This should only be used for physregs and 
   /// C_RegisterClass constraints.
   virtual std::vector<unsigned> 
-  getRegForInlineAsmConstraint(const std::string &Constraint) const;
+  getRegForInlineAsmConstraint(const std::string &Constraint,
+                               MVT::ValueType VT) const;
   
   /// isOperandValidForConstraint - Return true if the specified SDOperand is
   /// valid for the specified target constraint letter.