ARM assembly parsing of MUL instruction.

Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0cf9a4a042e2a756b650875b718887cc703d4eb1..89501dc0888b39d1fa7aca10aac98070da67a291 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
-  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
+  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
+      Mnemonic != "muls") {
     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
       .Case("eq", ARMCC::EQ)
       .Case("ne", ARMCC::NE)

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 00cfec9c7e67a1a5c825a519db0a270893404ccb..9fb90d23ee4a526463b06c2f7b07df0c385bc8f7 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -811,6 +811,20 @@ _func:
 @ CHECK: msr  SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
 @ CHECK: msr  CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
 
+@------------------------------------------------------------------------------
+@ MUL
+@------------------------------------------------------------------------------
+
+  mul r5, r6, r7
+  muls r5, r6, r7
+  mulgt r5, r6, r7
+  mulsle r5, r6, r7
+
+@ CHECK: mul   r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xe0]
+@ CHECK: muls  r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xe0]
+@ CHECK: mulgt r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xc0]
+@ CHECK: mulsle        r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xd0]
+
 @------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------