Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24648 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index f19f148d1aee10bcff056572b2e1b0922f811340..63cf7b2668b95a9e4fc45e016e99f60dfba0966d 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -394,6 +394,22 @@ public:
     Ops.push_back(Op5);
     return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
   }
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+                          MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+                          SDOperand Op3, SDOperand Op4, SDOperand Op5,
+                          SDOperand Op6) {
+    std::vector<MVT::ValueType> ResultTys;
+    ResultTys.push_back(VT1);
+    ResultTys.push_back(VT2);
+    std::vector<SDOperand> Ops;
+    Ops.push_back(Op1);
+    Ops.push_back(Op2);
+    Ops.push_back(Op3);
+    Ops.push_back(Op4);
+    Ops.push_back(Op5);
+    Ops.push_back(Op6);
+    return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+  }
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1, 
                           MVT::ValueType VT2, std::vector<SDOperand> &Ops) {
     std::vector<MVT::ValueType> ResultTys;

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a0f4d925c90a4d3e1ebcc49919c0ebdc7faa284a..bba3cb22305bd8a8c4afd2847d8bf86d26449bb6 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1165,11 +1165,14 @@ def ADD32rr  : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
 } // end isConvertibleToThreeAddress
 } // end isCommutable
 def ADD8rm   : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
-                 "add{b} {$src2, $dst|$dst, $src2}", []>;
+                 "add{b} {$src2, $dst|$dst, $src2}",
+                 [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>;
 def ADD16rm  : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+                 "add{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize;
 def ADD32rm  : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "add{l} {$src2, $dst|$dst, $src2}", []>;
+                 "add{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>;
 
 def ADD8ri   : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                    "add{b} {$src2, $dst|$dst, $src2}",